Patents by Inventor Chih-Wei Yang

Chih-Wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804402
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Shih-Wei Peng, Wei-Cheng Lin, Lei-Chun Chou
  • Patent number: 10802564
    Abstract: A system and method for compensating for voltage drops in a device having a remote node is disclosed. A power supply unit has an adjustable voltage output and a feedback circuit. A power path is coupled to the power supply unit to supply voltage to the remote node. A switch has an output coupled to the feedback circuit, a first input coupled to the power path, and a second input coupled to the remote node. A controller is coupled to the switch. The controller is operable to control the switch to switch between the inputs to cause the feedback circuit of the power supply unit to compensate the voltage output for a voltage drop on the power path or the remote node.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: October 13, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventor: Chih-Wei Yang
  • Patent number: 10804654
    Abstract: An electrical connector and a transmission wafer thereof are provided. The transmission wafer includes an insulating frame, a plurality of grounding terminals fixed to the insulating frame, and a shielding member disposed on the insulating frame. Each of the grounding terminals includes a middle grounding segment embedded in the insulating frame, a front grounding segment, and a rear grounding segment, the latter two of which respectively extend from two ends of the middle grounding segment in two different directions. The shielding member includes a grounding sheet disposed on the insulating frame and a plurality of elastic arms curvedly extending from the grounding sheet to protrude from the insulating frame. The elastic arms are respectively abutted against portions of the front grounding segments arranged adjacent to the insulating frame.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: October 13, 2020
    Assignee: TOPCONN ELECTRONIC (KUNSHAN) CO., LTD.
    Inventors: Chih-Wei Chen, Chung-Nan Pao, Yueh-Lin Yang, Yi-Guang Lai, Guo-Cing Chen, Kai Wu
  • Patent number: 10796759
    Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
  • Patent number: 10782536
    Abstract: A laser device for additive manufacturing and an operation method thereof are provided. The laser device has a laser generation unit, a spectroscopic unit, a control unit, and a lens assembly unit. A laser beam is split into two or more beams by disposing the spectroscopic unit and the lens assembly unit. Thus, a roughness of a process surface and a process time can be reduced.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 22, 2020
    Assignee: TONGTAI MACHINE & TOOL CO., LTD
    Inventors: Chung-wei Cheng, Chun-yu Tsai, Chih-hsiang Yang, Hsin-pao Chen, Jui-hsiung Yen
  • Patent number: 10784630
    Abstract: A female connector and a transmission wafer are provided. The female connector includes a housing and a plurality of transmission wafers inserted into the housing. Each of the transmission wafers includes an insulating frame, a plurality of grounding terminals fixed to the insulating frame, and a first shielding member and a second shielding member respectively disposed on two opposite sides of the insulating frame. In each of the transmission wafers, the second shielding member is disposed on a front end portion of the insulating frame, and the first and second shielding members are electrically connected to the grounding terminals so as to be electrically connected to each other through the grounding terminals. The second shielding member of one of any two adjacent transmission wafers is abutted against and electrically connected to the first shielding member of the other one of the any two adjacent transmission wafers.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 22, 2020
    Assignee: TOPCONN ELECTRONIC (KUNSHAN) CO., LTD.
    Inventors: Chih-Wei Chen, Chung-Nan Pao, Yueh-Lin Yang, Yu-Hsiung Lin, Kai Wu, Yan-Bo Lin
  • Publication number: 20200287332
    Abstract: A female connector and a transmission wafer are provided. The female connector includes a housing and a plurality of transmission wafers inserted into the housing. Each of the transmission wafers includes an insulating frame, a plurality of grounding terminals fixed to the insulating frame, and a first shielding member and a second shielding member respectively disposed on two opposite sides of the insulating frame. In each of the transmission wafers, the second shielding member is disposed on a front end portion of the insulating frame, and the first and second shielding members are electrically connected to the grounding terminals so as to be electrically connected to each other through the grounding terminals. The second shielding member of one of any two adjacent transmission wafers is abutted against and electrically connected to the first shielding member of the other one of the any two adjacent transmission wafers.
    Type: Application
    Filed: September 12, 2019
    Publication date: September 10, 2020
    Inventors: CHIH-WEI CHEN, CHUNG-NAN PAO, YUEH-LIN YANG, YU-HSIUNG LIN, KAI WU, YAN-BO LIN
  • Publication number: 20200287333
    Abstract: An electrical connector assembly, a female connector, and a male connector are provided. The electrical connector assembly includes a female connector and a male connector detachably inserted into the female connector. The female connector includes a housing and a plurality of transmission wafers inserted into the housing. Each of the transmission wafers includes an insulating frame and a plurality of grounding terminals fixed to the insulating frame. The male connector includes a carrier and a plurality of shielding terminals fixed to the carrier. Two side walls of each of the shielding terminals are respectively abutted against and electrically connected to two of the grounding terminals each having at least one first contacting portion.
    Type: Application
    Filed: September 12, 2019
    Publication date: September 10, 2020
    Inventors: CHIH-WEI CHEN, CHUNG-NAN PAO, YUEH-LIN YANG, YU-HSIUNG LIN, KAI WU
  • Patent number: 10763264
    Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: September 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang, Sho-Shen Lee
  • Patent number: 10756087
    Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 10745723
    Abstract: The present invention relates to a method for increasing polyhydroxyalkanoates (PHAs) content of waste sludge, by taking the fermentation liquid fermented from waste sludge as a carbon source, and performing ADF domestication process, thereby quickly raising PHAs contentin the waste sludge, in accordance with the method of the present invention, the conventional complicated domestication steps is simplified and a higher content PHAs can be produced, additionally the added carbon source of the present invention is the VFA fermented by the waste sludge, so it's unnecessary to add extra material, therefore including more industrial utilization.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: August 18, 2020
    Assignee: National Chi Nan University
    Inventors: Yung-Pin Tsai, Meng-Shan Lu, Chih-Chi Yang, Hao Shiu, Jan-Wei Lin, Yu-Wei Liou
  • Patent number: 10734321
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu, Shih-Ming Chang
  • Publication number: 20200243447
    Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.
    Type: Application
    Filed: April 20, 2020
    Publication date: July 30, 2020
    Inventors: Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Patent number: 10711263
    Abstract: The present invention provides a method for extracting polyhydroxyalkanoates (PHAs), which comprises a pre-process step and an extraction step: removing water from waste sludge containing microorganisms in the pre-process step so that the waste sludge containing microorganisms has a water content of less than 40%; and applying a high-voltage pulsed electric field to the waste sludge during the extraction step to destroy the microorganisms and release the PHAs, wherein the high-voltage pulsed electric field is between 50 volts and 400 volts, an application time of the high-voltage pulsed electric field is between 5 seconds and 90 seconds, and an application frequency of the high-voltage pulsed electric field is between 500 Hz and 1000 Hz, thereby extracting the PHAs in the case of few chemicals.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 14, 2020
    Assignee: NATIONAL CHI NAN UNIVERSITY
    Inventors: Yung-Pin Tsai, Meng-Shan Lu, Chih-Chi Yang, Hao Shiu, Jan-Wei Lin
  • Patent number: 10699956
    Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Chih-Liang Chen, Tzu-Chiang Chen, Ta-Pen Guo, Yu-Lin Yang, I-Sheng Chen, Szu-Wei Huang
  • Publication number: 20200203011
    Abstract: A virtual consultation method and an electronic device are provided. The method includes: receiving physiological information obtained through sensing a user by a sensing device; analyzing the physiological information to obtain an analysis result; adjusting weights of a plurality of questions according to the analysis result and determining a first question applicable to the user and an order of the first question according to the weights; and outputting the first question according to the order to simulate a question asked by a doctor for the user during consultation.
    Type: Application
    Filed: November 13, 2019
    Publication date: June 25, 2020
    Applicants: KURA Care LLC, KURA Med Inc.
    Inventors: Kai-Chieh Yang, Chih-Wei Chiu, Alvin Hsu
  • Patent number: 10684634
    Abstract: A system and method for detecting and compensating for temperature effects in a device having a power supply and a remote node. The system includes a power supply unit having an adjustable voltage output and a feedback circuit. The voltage output is adjusted based on the output of the feedback circuit. A power path is coupled to the power supply unit. The power path has power connectors to supply voltage from the power supply unit to a remote node. The remote node is operable to sense a voltage drop of the power path at the remote node associated with temperature effects on the power connectors. An adjustable resistor has an output coupled to the feedback circuit. A controller is coupled to the remote node and the adjustable resistor. The controller determines a resistance value to compensate for the temperature effects and sets the adjustable resistor to change the power output.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 16, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chih-Wei Yang, Chih-Hao Chang, Ching-Jung Liu
  • Publication number: 20200187378
    Abstract: A server chassis includes a housing and two support portions. A bottom plate of the housing includes a loading surface and a three-dimensional reinforcing pattern integrally formed on the loading surface for reinforcing the structural strength of the bottom plate. The support portions are respectively located on an outer surface of the sidewall of the housing. A coverage area of the three-dimensional reinforcing pattern is greater than 10% of the total area of the loading surface. The three-dimensional reinforcing pattern includes a plurality of texture patterns regularly reproduced on the loading surface toward a linear axial direction. A maximum height of each of the texture patterns is 0.5-0.8 mm.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 11, 2020
    Inventors: Kuang-Yun SHEN, Cheng-Feng YANG, Chih-Wei HOU
  • Publication number: 20200171655
    Abstract: An automatic control method and an automatic control device are provided. The automatic control device includes a processing unit, a memory unit and a camera unit. The memory unit records an object database and a behavior database. When the automatic control device is operated in an automatic learning mode, the camera unit obtains a continuous image, and the processing unit analyzes the continuous image to determine whether there is an object being moved and matching an object model recorded in the object database in a first placement area. When the continuous image displays the object is moved, the processing unit obtain control data corresponding to moving the object from the first placement area to a second placement area, and the processing unit records the control data to the behavior database. The control data includes trajectory data and motion posture data of the object.
    Type: Application
    Filed: November 21, 2019
    Publication date: June 4, 2020
    Applicant: Metal Industries Research & Development Centre
    Inventors: Shi-Wei Lin, Fu-I Chou, Chun-Ming Yang, Wei-Chan Weng, Chih-Chin Wen
  • Patent number: D896763
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: September 22, 2020
    Assignee: STARCONN ELECTRONIC (SU ZHOU) CO., LTD.
    Inventors: Chih-Wei Chen, Chung-Nan Pao, Yueh-Lin Yang, Yi-Guang Lai, Guo-Cing Chen, Kai Wu