Patents by Inventor Chih-Yang Chang
Chih-Yang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240124980Abstract: A bimetallic faceplate for substrate processing is provided including a plate having a plurality of gas distribution holes and formed of a first metal having a first coefficient of thermal expansion, the plate having at least one groove around a center of the plate and spaced from the center of the plate; and a metallic element disposed in the at least one groove and fixed to the plate in the at least one groove, the metallic element having a second coefficient of thermal expansion different from the first coefficient of thermal expansion, the metallic element being symmetrically arranged on or in the plate. A chamber for substrate processing is provided that includes a bimetallic faceplate. Also, a method of making a bimetallic faceplate is provided.Type: ApplicationFiled: October 12, 2022Publication date: April 18, 2024Inventors: Gaurav SHRIVASTAVA, Pavankumar Ramanand HARAPANHALLI, Sudhir R. GONDHALEKAR, Yao-Hung YANG, Chih-Yang CHANG
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Patent number: 11944021Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.Type: GrantFiled: March 15, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yang Chang, Wen-Ting Chu
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Patent number: 11889705Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.Type: GrantFiled: August 3, 2021Date of Patent: January 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
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Publication number: 20240026975Abstract: A sealing member includes a monolithic body including a first portion adjoining a second portion. The first portion forms part of a circle. The second portion includes first and second lobes. Each lobe adjoins the first portion with a concave surface. In one example, each lobe includes a rounded tip, and a convex surface extends from one rounded tip to the other rounded tip.Type: ApplicationFiled: June 28, 2023Publication date: January 25, 2024Inventors: Yao-Hung YANG, Chih-Yang CHANG, Sam Hyungsam KIM
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Patent number: 11856797Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.Type: GrantFiled: January 31, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Chieh Yang, Hsia-Wei Chen, Chih-Yang Chang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
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Publication number: 20230410931Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.Type: ApplicationFiled: June 21, 2022Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsiang CHEN, Chih-Yang CHANG, Chia Yu WANG, Meng-Chun SHIH
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Publication number: 20230410932Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.Type: ApplicationFiled: July 31, 2023Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsiang CHEN, Chih-Yang Chang, Chia Yu Wang, Meng-Chun Shih
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Publication number: 20230402304Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a processing volume for processing a substrate and a pressure system in fluid communication with the processing volume and comprising a throttle valve assembly including a housing, a sensing device disposed in an interior of the housing, and a fan open to the interior of the housing, wherein, during operation of the pressure system to control a pressure within the processing volume, the sensing device is responsive to temperature changes in the interior of the housing such that the fan remains off when a temperature of the interior of the housing is less than a predetermined temperature and automatically turns on when the temperature within interior of the housing is equal to or greater than the predetermined temperature.Type: ApplicationFiled: May 19, 2022Publication date: December 14, 2023Inventors: Gaurav SHRIVASTAVA, Pavankumar Ramanand HARAPANHALLI, Yao-Hung YANG, Sudhir R. GONDHALEKAR, Chih-Yang CHANG
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Patent number: 11844286Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.Type: GrantFiled: November 30, 2021Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
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Patent number: 11837312Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.Type: GrantFiled: June 21, 2022Date of Patent: December 5, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsiang Chen, Chih-Yang Chang, Chia Yu Wang, Meng-Chun Shih
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Publication number: 20230380190Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chieh-Fei CHIU, Wen-Ting CHU, Yong-Shiuan TSAIR, Yu-Wen LIAO, Chih-Yang CHANG, Chin-Chieh YANG
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Publication number: 20230354618Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element and a second RRAM element over a substrate. A conductive element is arranged below the first RRAM element and the second RRAM element. The conductive element electrically couples the first RRAM element to the second RRAM element. An upper insulating layer continuously extends over the first RRAM element and the second RRAM element. An upper inter-level dielectric (ILD) structure laterally surrounds the first RRAM element and the second RRAM element. The upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.Type: ApplicationFiled: July 6, 2023Publication date: November 2, 2023Inventors: Chin-Chieh Yang, Chih-Yang Chang, Wen-Ting Chu, Yu-Wen Liao
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Publication number: 20230333157Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.Type: ApplicationFiled: June 20, 2023Publication date: October 19, 2023Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang
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Patent number: 11751485Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.Type: GrantFiled: November 30, 2021Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
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Patent number: 11751405Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.Type: GrantFiled: September 25, 2020Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chieh-Fei Chiu, Wen-Ting Chu, Yong-Shiuan Tsair, Yu-Wen Liao, Chih-Yang Chang, Chin-Chieh Yang
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Publication number: 20230272855Abstract: An apparatus for inserting a seal member into a seal groove includes a tray. The tray includes a holding groove formed in a front surface for containing the seal member. The holding groove is sized and shaped to correspond with the seal groove. A method of installing a seal member into a seal groove includes aligning the holding groove with the seal groove, and applying a pressure to a back surface of the tray, thereby deforming the tray and inserting the seal member into the seal groove.Type: ApplicationFiled: June 28, 2022Publication date: August 31, 2023Inventors: Yao-Hung YANG, Fred Eric RUHLAND, Chih-Yang CHANG, Chiache LIN, Saurabh Murlidhar CHAUDHARI, Sridhar KENCHANAPURA NAGARAJU, Kishan RAO
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Patent number: 11737290Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.Type: GrantFiled: December 6, 2021Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chieh Yang, Chih-Yang Chang, Wen-Ting Chu, Yu-Wen Liao
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Patent number: 11726747Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data sate. The first random bit is then read from the MRAM cell.Type: GrantFiled: December 9, 2022Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Chih-Hui Weng, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang, Chia-Hsiang Chen
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Patent number: 11719742Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.Type: GrantFiled: August 8, 2022Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang
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Patent number: 11723292Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.Type: GrantFiled: June 24, 2020Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You