Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

Abstract: Disclosed is a self-powered formaldehyde sensing device, comprising: a triboelectric material electrode layer including a first substrate and a first electrode layer formed on the first substrate; a triboelectric material dielectric layer including a second substrate, a second electrode layer formed on the second substrate, a dielectric reacting layer formed on the second electrode layer, and a reaction modification layer formed on the dielectric reacting layer to surface-modify the dielectric reacting layer, the reaction modification layer being a phosphomolybdic acid complex (cPMA) layer, the phosphomolybdic acid complex of the phosphomolybdic acid complex layer being obtained by dissolving 4,4?-bipyridine (BPY) in isopropanol (IPA) and then mixing with phosphomolybdic acid (PMA) solution; an elastic spacer; and an external circuit.

Abstract: An anti-fuse structure includes an active area, a gate electrode over the active area, and a dielectric layer between the active area and the gate electrode. The active area and the gate electrode partially overlap in a vertical projection direction, forming a plurality of channels. One of the gate electrode and the active area includes a plurality of extending portions to form the plurality of channels.

Abstract: An electronic device includes a substrate, an electronic component disposed over the substrate and an electrical testing component disposed over the substrate. The electronic component includes a bottom plate over the substrate, and a top plate over the bottom plate. The electrical testing component includes a first anti-fuse structure and a second anti-fuse structure, wherein the first anti-fuse structure and the second anti-fuse structure are electrically connected to the bottom plate.

Abstract: An electronic device includes a substrate, an electronic component disposed over the substrate and an electrical testing component disposed over the substrate. The electronic component includes a bottom plate over the substrate, and a top plate over the bottom plate. The electrical testing component includes a first anti-fuse structure and a second anti-fuse structure, wherein the first anti-fuse structure and the second anti-fuse structure are electrically connected to the bottom plate.

Abstract: An anti-fuse structure includes an active area, a gate electrode over the active area, and a dielectric layer between the active area and the gate electrode. The active area and the gate electrode partially overlap in a vertical projection direction, forming a plurality of channels. One of the gate electrode and the active area includes a plurality of extending portions to form the plurality of channels.

Abstract: An anti-fuse structure includes an active area, a gate electrode over the active area, and a dielectric layer between the active area and the gate electrode. The active area and the gate electrode partially overlap in a vertical projection direction, forming a plurality of channels. One of the gate electrode and the active area includes a plurality of extending portions to form the plurality of channels.