Abstract: A circuit and method that optimizes and adapts the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. A high speed system can select either of a first or a second adaptation routine to handle changes in the bit and gain loadings of sub-channel carriers based on line disturbances or transmission change requests, based on which is most aptly suited to handle the particular change. In a preferred embodiment the resulting bit/energy loadings can be adjusted to be fully compliant with applicable Discrete Multi-Tone (DMT) implementations of Asymmetric Digital Subscriber Loop (ADSL) protocols.

Abstract: A circuit and method that optimizes a set up time and control of bit and energy loadings of data sub-channels in a multi-channel data transmission signal is disclosed. A time out period, or an iteration count are used to control a setup time. An initialization routine attempts to make appropriate loadings within such time out period or within an iteration count parameter. If it is unable to do so, a handoff is made to a second routine to complete the loadings. In a preferred embodiment the initialization routine calculates rough parameters, while the second routine finalizes the capacity calculations. Another aspect of the invention ensures that the initialization routine can be repeated at a later time to re-compute appropriate bit and energy loadings to ensure that significant changes caused by line disturbances or large data rate variations can be quickly accommodated.

Abstract: A process for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The inventive process is preferably embodied in an microcode routine executable by a high speed digital signal processor. The routine monitors, analyzes and stores sub-channel signal-to-noise characteristics, determines theoretical bit capacity loadings, evaluates power performance margins, and optimizes sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. Alternatively, for a given power performance margin, the achieved data rate can be maximized. To achieve these results, a number of non-zero bit sub-channels (N.sub.CH) are remembered from iteration to iteration, which results in a more optimal loading of the sub-channels. A unique new approach is also disclosed for deciding which of the sub-channels should be disabled to have a zero bit loading.

Abstract: A circuit for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The circuit preferably includes a high speed memory coupled to a digital signal processor running an executable routine for analyzing sub-channel signal-to-noise characteristics, determining theoretical bit capacity loadings, evaluating power performance margins, and optimizing sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. The circuit keeps track of the number of non-zero bit sub-channels (N.sub.CH) from iteration to iteration, which results in a more accurate loading of the sub-channels.

Abstract: An ADSL transceiver includes a new circuit and various iterative initialization and fine tuning routines for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal. The routines quickly converge to a target data rate by first estimating a power margin, and generating a bounded interval that includes the target rate. Thereafter, a binary iterative portion of the routine takes over and effectuates a final convergence to the target rate. A new mechanism for determining useful sub-channels is also disclosed. The resulting routines are extremely useful in that they maximize a data rate for a given power margin, and conversely, maximize a power margin for a given data rate. Two variants of a fine tuning process are also disclosed, and both can be used in combination to maximize system performance.

Abstract: A circuit for optimizing and adapting the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The circuit preferably includes a high speed memory coupled to a digital signal processor running an executable routine for analyzing sub-channel signal-to-noise characteristics, determining theoretical bit capacity loadings, evaluating power performance margins, and optimizing initial and adaptive sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. The circuit keeps track of the number of non-zero bit sub-channels (N.sub.CH) from iteration to iteration, which results in a more accurate loading of the sub-channels.

Abstract: An adaptive process for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The inventive process is preferably embodied in one or more microcode routines executable by a high speed digital signal processor. A first routine initializes the transmission system, while a second routine adaptively changes system parameters as necessary to accommodate channel performance changes, varying target bit rates, etc. Both of the routines monitor, analyze and store sub-channel signal-to-noise characteristics, determine theoretical bit capacity loading, evaluates power performance margin, and optimize sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. Alternatively, for a given power performance margin, the achieved data rate can be maximized. To achieve these results, a number of non-zero bit sub-channels (N.sub.