Patents by Inventor Chikara Watatani

Chikara Watatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250056943
    Abstract: A semiconductor device according to the present disclosure includes: a semiconductor substrate; a first semiconductor layer formed on the semiconductor substrate; an insulating film formed on the first semiconductor layer; and a connecting electrode including a front surface electrode formed in contact with the insulating film and having a plurality of opening portions that expose the insulating film on the bottom surface, and a plating film formed in contact with the front surface electrode and covering the opening portions.
    Type: Application
    Filed: March 1, 2022
    Publication date: February 13, 2025
    Applicant: Mitsubishi Electric Corporation
    Inventor: Chikara WATATANI
  • Publication number: 20220344893
    Abstract: Provided here are: semiconductor layers comprised of an n-type cladding layer formed on a surface of an n-type GaAs substrate, active layers formed on surfaces of the n-type cladding layer, p-type cladding layers formed on surfaces of the active layers, and p-type contact layers formed on surfaces of the p-type cladding layers, the p-type cladding layers and the p-type contact layers being formed to have a ridges; insulating films covering surfaces of the semiconductor layers but having openings on surfaces of the p-type contact layer; and conductive layers connected to the p-type contact layers through the openings, the conductive layers being formed on surfaces of the insulating films to cover planar portions provided in the semiconductor layers adjacently to the ridges; wherein, together with the conductive layers, convex sidewalls are provided to be placed over portions of the planar portions at their sides nearer to the ridges.
    Type: Application
    Filed: December 4, 2019
    Publication date: October 27, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Chikara WATATANI, Motoharu MIYASHITA, Takehiro NISHIDA
  • Patent number: 9171760
    Abstract: A method of manufacturing a semiconductor device includes: forming electrodes on a first major surface of a semiconductor substrate having first and second major surfaces facing in opposite directions; and forming a cleavage-inducing pattern on the first major surface of the semiconductor substrate. The cleavage-inducing pattern extends over a target cleavage position located between the electrodes, has a recess extending over the target cleavage position, and is made of a material different from the material of the semiconductor substrate. The method includes forming a scribed groove in the second major surface of the semiconductor substrate and in a position facing the target cleavage position; and cleaving the semiconductor substrate having the scribed groove and the cleavage-inducing pattern by applying pressure, through a cleaving blade, to the first major surface of the semiconductor substrate.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: October 27, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Chikara Watatani, Masato Negishi
  • Publication number: 20150118827
    Abstract: A method of manufacturing a semiconductor device includes: forming electrodes on a first major surface of a semiconductor substrate having first and second major surfaces facing in opposite directions; and forming a cleavage-inducing pattern on the first major surface of the semiconductor substrate. The cleavage-inducing pattern extends over a target cleavage position located between the electrodes, has a recess extending over the target cleavage position, and is made of a material different from the material of the semiconductor substrate. The method includes forming a scribed groove in the second major surface of the semiconductor substrate and in a position facing the target cleavage position; and cleaving the semiconductor substrate having the scribed groove and the cleavage-inducing pattern by applying pressure, through a cleaving blade, to the first major surface of the semiconductor substrate.
    Type: Application
    Filed: July 3, 2014
    Publication date: April 30, 2015
    Inventors: Chikara Watatani, Masato Negishi
  • Patent number: 8457451
    Abstract: A semiconductor optical element having a mesa structure formed by wet etching, includes a mesa structure having a ridge-type mesa structure or a high-mesa-type mesa structure, the mesa structure being disposed on a semiconductor substrate, and an extended mesa on the semiconductor substrate, the extended mesa being connected to a corner of the mesa structure and being the same material as the mesa structure.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: June 4, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeshi Yamatoya, Yoshimichi Morita, Chikara Watatani
  • Patent number: 7876799
    Abstract: A semiconductor laser (a first semiconductor optical device) and an optical modulator (a second semiconductor optical device) are integrated on the same n-type InP substrate. The semiconductor laser butt-joined to the optical modulator. Each of the semiconductor laser and the optical modulator has a Be-doped p-type InGaAs contact layer. The p-type InGaAs contact layers have a Be-doping concentration of 7×1018 cm?3 or more, and a thickness of 300 nm or less.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: January 25, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeshi Yamatoya, Chikara Watatani
  • Patent number: 7855096
    Abstract: A semiconductor film is formed on a GaAs substrate (semiconductor substrate). An SiO2 film (insulating film) is formed on the semiconductor film, and the SiO2 film is patterned. The semiconductor film is etched using the SiO2 film as a mask to form a mesa structure. The surface of the SiO2 film is treated by ashing, using SF6 gas (fluorine-containing gas), to terminate the surface of the SiO2 film with fluorine. The mesa structure is selectively buried with a III-V compound semiconductor film, using the SiO2 film having the surface that has been terminated by fluorine, as a mask.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: December 21, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Chikara Watatani, Toru Takiguchi
  • Publication number: 20100316080
    Abstract: A semiconductor optical element includes a p-type InP substrate doped with Zn; and a diffusion blocking layer doped with Ru, a p-type InP cladding layer, an active layer, and an n-type InP cladding layer sequentially arranged on the p-type InP substrate.
    Type: Application
    Filed: February 5, 2010
    Publication date: December 16, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Harunaka Yamaguchi, Chikara Watatani, Masayoshi Takemi
  • Publication number: 20100272389
    Abstract: A semiconductor optical element having a mesa structure formed by wet etching, includes a mesa structure having a ridge-type mesa structure or a high-mesa-type mesa structure, the mesa structure being disposed on a semiconductor substrate, and an extended mesa on the semiconductor substrate, the extended mesa being connected to a corner of the mesa structure and being the same material as the mesa structure.
    Type: Application
    Filed: January 21, 2010
    Publication date: October 28, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi Yamatoya, Yoshimichi Morita, Chikara Watatani
  • Patent number: 7816160
    Abstract: The present invention includes forming an optical guide layer on a substrate, forming a cap layer on the optical guide layer, and forming openings in parts of the optical guide layer and the cap layer to form a diffraction grating from part of the optical guide layer. The substrate is heated to a temperature less than a growth temperature of the cap layer and equal to at least a temperature at which mass transport of the cap layer occurs to cover, with part of the cap layer, the lateral faces of the optical guide layer exposed by the openings. A burying layer burying the diffraction grating is formed on the substrate, after the mass transport.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: October 19, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Chikara Watatani, Takashi Nagira
  • Patent number: 7720123
    Abstract: A buried type semiconductor laser 1 is made of a p-type InP substrate 2 and includes a ridge section 6 made up of a p type InP first clad layer 3, AlGaInAs distorted quantum well active layer 4 and n type InP second clad layer 5 laminated one atop another. On both sides of the ridge section 6, an buried current block layer 10 made up of a p-type InP first buried layer 7, n-type InP second buried layer 8 and semi-insulating Fe-doped InP third buried layer 9 laminated one atop another is formed. A top face of the third buried layer 9 is covered with an n-type InP semiconductor layer 11. The above structure can suppress the occurrence of a leakage current path on the top face of the third buried layer 9 and improve reliability of the buried type semiconductor laser.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: May 18, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tohru Takiguchi, Chikara Watatani
  • Patent number: 7656921
    Abstract: A current blocking structure of a semiconductor laser includes a p-type InP buried layer, an n-type InP current blocking layer, and a p-type InP current blocking layer laminated along the mesa side surface of a ridge. In the structure, an upper end part of the n-type InP current blocking layer is covered with the p-type InP buried layer and the p-type InP current blocking layer. The n-type InP current blocking layer is prevented from contacting n-type and p-type InP cladding layers. Creation of an ineffective current path from one of the n-type InP cladding layers through the n-type InP current blocking layer to a p-type InP cladding layer of the semiconductor laser is prevented.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: February 2, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Chikara Watatani
  • Publication number: 20090246903
    Abstract: The present invention includes forming an optical guide layer on a substrate, forming a cap layer on the optical guide layer, and forming openings in parts of the optical guide layer and the cap layer to form a diffraction grating from part of the optical guide layer. The substrate is heated to a temperature less than a growth temperature of the cap layer and equal to at least a temperature at which mass transport of the cap layer occurs to cover, with part of the cap layer, the lateral faces of the optical guide layer exposed by the openings. A burying layer burying the diffraction grating is formed on the substrate, after the mass transport.
    Type: Application
    Filed: August 29, 2008
    Publication date: October 1, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Chikara WATATANI, Takashi NAGIRA
  • Publication number: 20090166807
    Abstract: A semiconductor laser (a first semiconductor optical device) and an optical modulator (a second semiconductor optical device) are integrated on the same n-type InP substrate. The semiconductor laser butt-joined to the optical modulator. Each of the semiconductor laser and the optical modulator has a Be-doped p-type InGaAs contact layer. The p-type InGaAs contact layers have a Be-doping concentration of 7×1018 cm?3 or more, and a thickness of 300 nm or less.
    Type: Application
    Filed: April 8, 2008
    Publication date: July 2, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi Yamatoya, Chikara Watatani
  • Patent number: 7550304
    Abstract: A method for manufacturing a semiconductor laser element includes forming a semiconductor laminated structure, having an active layer, on a substrate; etching the semiconductor laminated structure to form a mesa; exposing the mesa to an oxygen-containing ambient forming an oxide layer on the mesa; removing a first part of the oxide layer from the mesa at a temperature lower than a critical temperature at which bonds between atoms of the oxide layer become stronger, by etching with a gas; removing the remainder of the oxide layer from the mesa at a temperature higher than the critical temperature by etching with a gas; and forming a burying layer coating the mesa.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: June 23, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takashi Nagira, Chikara Watatani
  • Patent number: 7544535
    Abstract: The method for manufacturing a semiconductor laser element according to the present invention has the steps of: forming a semiconductor laminated structure having an active layer composed of a semiconductor material containing Al; etching the semiconductor laminated structure to form a mesa; forming a first burying layer at a first growing temperature so as to coat the side of the mesa; and forming a second burying layer at a second growing temperature higher than the first growing temperature on the first burying layer to bury the circumference of the mesa.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: June 9, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Chikara Watatani, Toru Ota, Takashi Nagira
  • Publication number: 20090087966
    Abstract: A semiconductor film is formed on a GaAs substrate (semiconductor substrate). An SiO2 film (insulating film) is formed on the semiconductor film, and the SiO2 film is patterned. The semiconductor film is etched using the SiO2 film as a mask to form a mesa structure. The surface of the SiO2 film is treated by ashing, using SF6 gas (fluorine-containing gas), to terminate the surface of the SiO2 film with fluorine. The mesa structure is selectively buried with a III-V compound semiconductor film, using the SiO2 film having the surface that has been terminated by fluorine, as a mask.
    Type: Application
    Filed: February 20, 2008
    Publication date: April 2, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Chikara Watatani, Toru Takiguchi
  • Publication number: 20080054277
    Abstract: The semiconductor laser device includes an active layer, a p-type cladding layer, and a p-type cap layer. The layers are sequentially stacked so that the semiconductor laser device is provided. The p-type cap layer includes both a p-type dopant and an n-type dopant. In another aspect, the p-type cap layer includes a first layer including a first p-type dopant and a second layer including a second p-type dopant having a diffusion coefficient smaller than that of the first p-type dopant. The first layer is far from the active layer, and the second layer is close to the active layer. In further aspect, the p-type cap layer includes carbon (C) as a p-type dopant. According to these configuration, the p-type dopant can be prevented from being diffused in the active layer and the p-type cladding layer.
    Type: Application
    Filed: October 25, 2007
    Publication date: March 6, 2008
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Masayoshi Takemi, Kenichi Ono, Yoshihiko Hanamaki, Chikara Watatani, Tetsuya Yagi, Harumi Nishiguchi, Motoko Sasaki, Shinji Abe, Yasuaki Yoshida
  • Publication number: 20080050850
    Abstract: A method for manufacturing a semiconductor laser element includes forming a semiconductor laminated structure, having an active layer, on a substrate; etching the semiconductor laminated structure to form a mesa; cleaning the side of the mesa at a temperature lower thank a critical temperature at which an oxide layer forms on the side of the mesa using an etching gas; cleaning the side of the mesa at a temperature higher than the critical temperature using an etching gas; and forming a burying layer coating the side of the mesa after cleaning the side of the mesa.
    Type: Application
    Filed: January 19, 2007
    Publication date: February 28, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takashi NAGIRA, Chikara WATATANI
  • Publication number: 20080049805
    Abstract: A semiconductor laser includes a p-type InP substrate and a ridge section of a p type InP first cladding layer, an AlGaInAs strained quantum well active layer and a n type InP second cladding layer, laminated one atop the other. On both sides of the ridge section, a current blocking layer including a p-type InP first burying layer, an n-type InP second burying layer, and a semi-insulating Fe-doped InP third burying layer are laminated, one atop the other. A top face of the third burying layer is covered with an n-type InP semiconductor layer. This structure suppresses leakage current on the top face of the third burying layer and improves reliability of the semiconductor laser.
    Type: Application
    Filed: December 18, 2006
    Publication date: February 28, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tohru TAKIGUCHI, Chikara WATATANI