Patents by Inventor Chin Chang

Chin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190255012
    Abstract: This invention is announcing a composition of flavonoid skeleton in the formula I or formula II compound, wherein each of the substituents is given the definition as set forth in the specification and claims. This composition has the capacity to treating or preventing a virus infection in a subject.
    Type: Application
    Filed: December 21, 2018
    Publication date: August 22, 2019
    Applicant: Kaohsiung Medical University
    Inventors: Hui-Chun WANG, Yang-Chang Wu, Fang-Rong Chang, Chin-Chung WU
  • Patent number: 10388239
    Abstract: A display may have an array of light-emitting diode pixels or pixels containing portions of a liquid crystal layer to which electric fields are applied using electrodes. A pixel with a light-emitting diode may have a drive transistor coupled in series with the light-emitting diode. A storage capacitor may be coupled to a gate of the drive transistor. A pixel with a liquid crystal portion may have a storage capacitor coupled to a given one of the electrodes in that pixel. Switching circuitry in each pixel may be used to load data from a data line into the storage capacitor of the pixel. The switching circuitry may include a semiconducting-oxide transistor coupled to an associated data line and a series-connected silicon transistor that is coupled to the storage capacitor.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 20, 2019
    Assignee: Apple Inc.
    Inventors: Chin-Wei Lin, Jungbae Kim, Kyung Wook Kim, Minkyu Kim, Shih Chang Chang, Vasudha Gupta, Young Bae Park
  • Publication number: 20190250522
    Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Jui-Ching WU, Jeng-Horng CHEN, Chia-Chen CHEN, Shu-Hao CHANG, Shang-Chieh CHIEN, Ming-Chin CHIEN, Anthony YEN
  • Patent number: 10379155
    Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: August 13, 2019
    Assignee: XILINX, INC.
    Inventors: Ping-Chin Yeh, John K. Jennings, Rhesa Nathanael, Nui Chong, Cheang-Whang Chang, Daniel Y Chung
  • Patent number: 10381381
    Abstract: A display may have an array of pixels with light-emitting diodes that emit light to form images. The display may have a substrate with thin-film transistor circuitry for supplying signals to the light-emitting diodes. Anodes may be formed on the thin-film transistor circuitry, emissive material may be formed on the anodes, and a cathode layer may overlap the anodes. During operation, currents may flow between the anodes and the cathode layer to illuminate the diodes. An array of electrical components such as an array of light sensors in an integrated circuit may be mounted under the substrate. An array of corresponding light transmitting windows may be formed in the display each of which may allow light to pass through the display to a corresponding one of the light sensors. Light transmitting windows may be formed by patterning the cathode layer and supplying the windows with antireflection layers.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 13, 2019
    Assignee: Apple Inc.
    Inventors: Minhyuk Choi, Bhadrinarayana Lalgudi Visweswaran, Cheng Chen, Chin-Wei Lin, Meng-Huan Ho, Rui Liu, Shih Chang Chang, Soojin Park, Sarfaraz Moh, Jungmin Lee, John Z. Zhong
  • Patent number: 10378995
    Abstract: An optical wavefront testing system includes a light source, an image capturing unit and a processing unit. The image capturing unit includes a lens array and a sensor module that is configured to detect light rays passing through an optical element and the lens array. The processing unit controls the sensor module to detect the light rays under a plurality exposure conditions for generating a plurality of images each including a plurality of light spots, obtains a plurality of light spot datasets corresponding to the light spots and each including a plurality of pixel coordinate sets and a plurality of pixel values, and obtains wavefront information associated with the light spots based on the light spot datasets of at least two of the images.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 13, 2019
    Assignee: Tonta Electro Optical Co., Ltd.
    Inventors: Chao-Wen Liang, Chin-Chang Liang
  • Publication number: 20190237454
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Application
    Filed: August 1, 2018
    Publication date: August 1, 2019
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20190232520
    Abstract: A power miter saw includes two linear guide mechanisms each including a first link including a bifurcated first end including two opposite first through holes; and a bifurcated second end including two opposite second through holes; a spring-loaded second link including a bifurcated first end having two opposite first through hole having a bearing recess, and a bifurcated second end including two opposite second through holes; two washers at outer ends of the first through holes of the second link respectively; a cylindrical lining in the first through holes of the second link; two bearings each at the bearing recess; and a pivot driven through the first through holes of the first link, the washers, the bearings, the cylindrical lining, and the first through holes of the second link to receive a portion of a complimentary pivot to pivotably secure the first and second links together.
    Type: Application
    Filed: April 6, 2019
    Publication date: August 1, 2019
    Inventor: Chin-Chin Chang
  • Publication number: 20190221570
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.
    Type: Application
    Filed: February 14, 2018
    Publication date: July 18, 2019
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Tzu-Chin Wu, Wei-Lun Hsu
  • Publication number: 20190222940
    Abstract: A piezoelectric transducer including a substrate, a piezoelectric layer and a stiffening structure is provided. The substrate has a chamber. The piezoelectric layer has a displacement zone, a plurality of sensing zones, a plurality of gaps, a plurality of top electrodes, and a plurality of bottom electrodes. The displacement zone is located over the chamber. The sensing zones are surroundingly connected to an outer edge of the displacement zone and are located over the chamber. The gaps are each formed between any adjacent two of the plurality of sensing zones, and each of the gaps communicates with the chamber. The top electrodes are each disposed on a top surface of each of the sensing zones. The bottom electrodes are each disposed on a bottom surface of each of the sensing zones. The stiffening structure is disposed on a bottom of the displacement zone.
    Type: Application
    Filed: March 7, 2018
    Publication date: July 18, 2019
    Applicant: Merry Electronics(Shenzhen) Co., Ltd.
    Inventors: Jen-Yi Chen, Chao-Sen Chang, Kai-Yu Jiang, Jui-Chin Peng
  • Patent number: 10350726
    Abstract: The present disclosure relates to a chemical mechanical polishing (CMP) system, and an associated method to perform a CMP process. In some embodiments, the CMP system has a rotatable wafer carrier configured to hold a wafer face down to be processed. The CMP system also has a polishing layer attached to a polishing platen and having a front surface configured to interact with the wafer to be processed, and a CMP dispenser configured to dispense a slurry between an interface of the polishing layer and the wafer. The slurry contains charged abrasive particles therein. The CMP system also has a film electrode attached to a back surface of the polishing layer opposite to the front surface. The film electrode is configured to affect movements of the charged abrasive particles through applying an electrical field during the operation of the CMP system.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Wei Liang, Hsun-Chung Kuang, Yen-Chang Chu
  • Patent number: 10354974
    Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 16, 2019
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Andrew C. Chang, Tao Cheng
  • Patent number: 10354585
    Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 16, 2019
    Assignee: Apple Inc.
    Inventors: Chin-Wei Lin, Hung Sheng Lin, Shih Chang Chang, Shinya Ono
  • Publication number: 20190210241
    Abstract: A power miter saw includes a rotatable table on a base; a saw blade and motor mechanism; and two linear guide mechanisms each interconnecting the table and the saw blade and motor mechanism. The linear guide mechanism is provided with a first link, a spring biased second link pivotably secured to the first link, a fastener for fastening the second link and the positioning seat together; a projection on the first link; and a latch pivotably secured onto the second link and including first and second slots. In a first locked position, the second slot is placed on the projection. In a second locked position, the first slot is placed on the projection.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Inventor: Chin-Chin Chang
  • Publication number: 20190204730
    Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.
    Type: Application
    Filed: December 20, 2018
    Publication date: July 4, 2019
    Inventors: Yun-Yue LIN, Hsuan-Chen CHEN, Chih-Cheng LIN, Hsin-Chang LEE, Yao-Ching KU, Wei-Jen LO, Anthony YEN, Chin-Hsiang LIN, Mark CHIEN
  • Publication number: 20190206982
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Publication number: 20190206321
    Abstract: A display has rows and columns of pixels (22). A data line (Dn) in each column provides image data signals to the pixels of that column. Each row has first and second control lines (select[m], monitor[m]) coupled to the gates of first and second respective transistors (SE, MO) in each pixel. A third transistor in each pixel serves as a drive transistor (DR) and is coupled in series with a light-emitting diode (30) between positive and ground power supply voltages (VDD, VSS). A display driver circuitry in the display characterizes each of the light-emitting diodes in a column using the data line in an adjacent column from that light-emitting diode. Each of the drive transistors in a column is characterized using the data line in that column and the data line in an adjacent column.
    Type: Application
    Filed: August 10, 2017
    Publication date: July 4, 2019
    Inventors: Cheuk Chi Lo, Chin-Wei Lin, Chun-Yao Huang, Shih Chang Chang
  • Publication number: 20190196322
    Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Inventors: Chin-Hsiang Lin, Chien-Cheng Chen, Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Yih-Chen Su, Gaston Lee, Tran-Hui Shen
  • Publication number: 20190197954
    Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.
    Type: Application
    Filed: February 28, 2019
    Publication date: June 27, 2019
    Inventors: Chin-Wei Lin, Hung Sheng Lin, Shih Chang Chang, Shinya Ono
  • Publication number: 20190192536
    Abstract: Biocompatible microparticles include an ophthalmically active cyclic lipid component and a biodegradable polymer that is effective, when placed into the subconjunctival space, in facilitating release of the cyclic lipid component into the anterior and posterior segments of an eye for an extended period of time. The cyclic lipid component can be associated with a biodegradable polymer matrix, such as a matrix of a two biodegradable polymers. Or, the cyclic lipid component can be encapsulated by the polymeric component. The present microparticles include oil-in-water emulsified microparticles. The subconjunctivally administered microparticles can be used to treat or to reduce at least one symptom of an ocular condition, such as glaucoma or age related macular degeneration.
    Type: Application
    Filed: August 31, 2018
    Publication date: June 27, 2019
    Inventors: James Chang, Patrick Hughes, Chin-Ming Chang