Patents by Inventor Chin-Ching Huang

Chin-Ching Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11672819
    Abstract: Provided is a nanogel exhibiting anticoagulation and antioxidation activities, including a graphene-like nanosheet and a polysaccharide, which are complexed to form a cross-linked supramolecular structure. Also provided is a method of preparing the nanogel, including carbonizing the polysaccharide by dry heating. By the heating process, at least a portion of the polysaccharide is conversed into the graphene-like nanosheet, thereby forming a graphene-like nanosheet-embedded phenolic-polysaccharide nanogel that has exceptional polyphenolic structure and high binding affinity toward thrombin. Further provided is a method of preventing or treating a disease or a condition susceptible to amelioration by anticoagulants or antioxidants by using the nanogel.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: June 13, 2023
    Assignee: NATIONAL TAIWAN OCEAN UNIVERSITY
    Inventors: Ju-Yi Mao, Chin-Ching Huang, Han-Jia Lin
  • Publication number: 20220249541
    Abstract: Provided is a nanogel exhibiting anticoagulation and antioxidation activities, including a graphene-like nanosheet and a polysaccharide, which are complexed to form a cross-linked supramolecular structure. Also provided is a method of preparing the nanogel, including carbonizing the polysaccharide by dry heating. By the heating process, at least a portion of the polysaccharide is conversed into the graphene-like nanosheet, thereby forming a graphene-like nanosheet-embedded phenolic-polysaccharide nanogel that has exceptional polyphenolic structure and high binding affinity toward thrombin. Further provided is a method of preventing or treating a disease or a condition susceptible to amelioration by anticoagulants or antioxidants by using the nanogel.
    Type: Application
    Filed: February 8, 2021
    Publication date: August 11, 2022
    Inventors: Ju-Yi Mao, Chin-Ching Huang, Han-Jia Lin
  • Patent number: 10714528
    Abstract: A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 14, 2020
    Assignee: XINTEC INC.
    Inventors: Hsin Kuan, Shih-Kuang Chen, Chin-Ching Huang, Chia-Ming Cheng
  • Patent number: 10347616
    Abstract: A chip package includes a sensing chip, a computing chip, and a protective layer annularly surrounding the sensing chip and the computing chip. The sensing chip has a first conductive pad, a sensing element, a first surface and a second surface opposite to each other. And the sensing element is disposed on the first surface. The computing chip has a second conductive pad and a computing element. The protective layer is formed by lamination and at least exposes the sensing element. The chip package further includes a conductive layer underneath the second surface of the sensing chip and extending to be in contact with the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 9, 2019
    Assignee: XINTEC INC.
    Inventors: Hsin Kuan, Chin-Ching Huang, Chia-Ming Cheng
  • Publication number: 20190140012
    Abstract: A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 9, 2019
    Inventors: Hsin KUAN, Shih-Kuang CHEN, Chin-Ching HUANG, Chia-Ming CHENG
  • Publication number: 20170330871
    Abstract: A chip package includes a sensing chip, a computing chip, and a protective layer annularly surrounding the sensing chip and the computing chip. The sensing chip has a first conductive pad, a sensing element, a first surface and a second surface opposite to each other. And the sensing element is disposed on the first surface. The computing chip has a second conductive pad and a computing element. The protective layer is formed by lamination and at least exposes the sensing element. The chip package further includes a conductive layer underneath the second surface of the sensing chip and extending to be in contact with the first conductive pad and the second conductive pad.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 16, 2017
    Inventors: Hsin KUAN, Chin-Ching HUANG, Chia-Ming CHENG
  • Patent number: 7884467
    Abstract: A kind of microphone package structure includes at least of a substrate, a sound processing unit, an upper cap and other devices. There would be at least one trench set on the substrate, and a separation gap between the trench and the bonding pad of the substrate is maintained. After connective paste is smeared on the surface of the substrate, the trench would be assembled with other devices. This kind of package structure could prevent a short circuit being caused by the overflowing of the connective paste.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: February 8, 2011
    Assignee: Lingsen Precision Industries, Ltd.
    Inventors: Chin-Ching Huang, Jiung-Yue Tien, Hsi-Chen Yang
  • Patent number: 7511373
    Abstract: A cap package for MEMS includes a substrate having a connection zone that is grounded, a chip mounted on the substrate, a cap capped on the substrate and provided with a through hole corresponding to the chip, and a conducting glue made of a non-metal material having a resistivity smaller than 102 ?m. The conducting glue is applied on the connection zone of the substrate and sandwiched between the cap and the substrate for electrically connecting the cap with the substrate.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: March 31, 2009
    Assignee: Lingsen Precision Inductries, Ltd.
    Inventors: Jiung-Yue Tien, Ming-Te Tu, Chin-Ching Huang
  • Publication number: 20080285784
    Abstract: A kind of microphone package structure includes at least of a substrate, a sound processing unit, an upper cap and other devices. There would be at least one trench set on the substrate, and a separation gap between the trench and the bonding pad of the substrate is maintained. After connective paste is smeared on the surface of the substrate, the trench would be assembled with other devices. This kind of package structure could prevent a short circuit being caused by the overflowing of the connective paste.
    Type: Application
    Filed: July 18, 2008
    Publication date: November 20, 2008
    Inventors: Chin-Ching Huang, Jiung-Yue Tien, Hsi-Chen Yang
  • Publication number: 20080164602
    Abstract: A cap package for MEMS includes a substrate, a cap made of a carbon added plastic material and capped on the substrate to define with the substrate an accommodation chamber, and a chip mounted on the substrate and located inside the accommodation chamber. The substrate has a conducting portion electrically connected with the cap and grounded.
    Type: Application
    Filed: June 21, 2007
    Publication date: July 10, 2008
    Applicant: Lingsen Precision Industries, Ltd.
    Inventors: Jiung-Yue TIEN, Ming-Te Tu, Chin-Ching Huang
  • Publication number: 20080164594
    Abstract: A cap package for MEMS includes a substrate having a connection zone that is grounded, a chip mounted on the substrate, a cap capped on the substrate and provided with a through hole corresponding to the chip, and a conducting glue made of a non-metal material having a resistivity smaller than 102 ?m. The conducting glue is applied on the connection zone of the substrate and sandwiched between the cap and the substrate for electrically connecting the cap with the substrate.
    Type: Application
    Filed: June 21, 2007
    Publication date: July 10, 2008
    Applicant: Lingsen Precision Industries, Ltd.
    Inventors: Jiung-Yue TIEN, Ming-Te Tu, Chin-Ching Huang
  • Publication number: 20080164583
    Abstract: A cap package includes a substrate on which a chip is mounted. A cap is made of silicon doped with non-metal dopant. The cap is capped on the substrate to define with the substrate an accommodation chamber that receives the chip inside. The chip is electrically connected with a conducting portion of the substrate which is grounded.
    Type: Application
    Filed: June 18, 2007
    Publication date: July 10, 2008
    Applicant: Lingsen Precision Industries, Ltd.
    Inventors: Jiung-Yue Tien, Ming-Te Tu, Chin-Ching Huang
  • Publication number: 20080079141
    Abstract: A MEMS module package includes a housing with an accommodation chamber and an opening in communication with the accommodation chamber. The housing has a substrate and an electrically insulative cap capped on the substrate and defining with the substrate the accommodation chamber therebetween. A micro electro-mechanical chip is installed on the substrate and located inside the accommodation chamber. The micro electro-mechanical chip has an action zone corresponding to the opening of the housing. A first conducting layer and a second conducting layer are respectively disposed on an inner surface and an outer surface of the electrically insulative cap.
    Type: Application
    Filed: June 29, 2007
    Publication date: April 3, 2008
    Applicant: Lingsen Precision Industries, Ltd.
    Inventors: Jiung-Yue Tien, Ming-Te Tu, Chin-Ching Huang
  • Publication number: 20070182002
    Abstract: A kind of microphone package structure is disclosed. It comprises at least of a substrate, a sound processing unit, an upper cap and other devices. There would be at least one trench set on the substrate, and a separation gap between the trench and the bounding pad of the substrate is maintained. After connective paste is smeared on the surface of the substrate, the trench would be assembled with other devices. This kind of package structure could prevent a short circuit being caused by the overflowing of the connective paste.
    Type: Application
    Filed: March 29, 2006
    Publication date: August 9, 2007
    Inventors: Chin-Ching Huang, Jiung-Yue Tien, Hsi-Chen Yang
  • Publication number: 20070165898
    Abstract: An acoustic head structure for a microphone is disclosed. It comprises a substrate, a sound-processing unit and an upper cap. The upper cap has a plurality of acoustic holes that are through-holes arranged about the upper lid. The position and shape of the acoustic holes can prevent foreign matter like dust from falling into the acoustic head structure.
    Type: Application
    Filed: March 29, 2006
    Publication date: July 19, 2007
    Inventors: Chin-Ching Huang, Min-Te Tu, Jiung-Yue Tien
  • Patent number: 6047467
    Abstract: A method for minimizing signal delays caused by mismatch in length of the inner leads of a package lead frame. This is accomplished by the provision of a unique conductive trace pattern formed preferably on the top surface or else on a lower surface of an electrically-insulated, heat-conducting printed circuit board. The conductive trace pattern includes a plurality of U-shaped metallized traces. Each of the plurality of U-shaped traces have a varying length so that certain ones adjacent the inner leads at the center of the package lead frame are longer than certain ones adjacent the inner leads at the corners of the package lead frame. The conductive trace pattern and the outer leads of the package lead frame also serve to transfer heat away from a molded-plastic body encapsulating an integrated-circuit die and the package lead frame and distribute the same on the printed circuit board.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: April 11, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Ahmad B. Hamzehdoost, Chin-Ching Huang
  • Patent number: 5742009
    Abstract: A printed circuit board layout is provided for minimizing signal delays caused by mismatch in length of the inner leads of a package lead frame. This is accomplished by the provision of a unique conductive trace pattern formed preferably on the top surface or else on a lower surface of an electrically-insulated, heat-conducting printed circuit board. The conductive trace pattern includes a plurality of U-shaped metallized traces. Each of the plurality of U-shaped traces have a varying length so that certain ones adjacent the inner leads at the center of the package lead frame are longer than certain ones adjacent the inner leads at the corners of the package lead frame. The conductive trace pattern and the outer leads of the package lead frame also serve to transfer heat away from a molded-plastic body encapsulating an integrated-circuit die and the package lead frame and distribute the same on the printed circuit board.
    Type: Grant
    Filed: October 12, 1995
    Date of Patent: April 21, 1998
    Assignee: VLSI Technology Corporation
    Inventors: Ahmad Hamzehdoost, Chin-Ching Huang
  • Patent number: 5641988
    Abstract: A multi-layered, high performance integrated circuit package is disclosed having a number of design features which increase the performance and manufacturability of the integrated circuit package, and reduce the effects of parasitic noise generated within the package. The metallic layers connecting contact fingers formed on ledges around the periphery of a die cavity area, to their respective package pins are organized such that a ground metallic layer is interposed between each pair of input/output signal metallic layers, and each input/output signal metallic layer is sandwiched between a pair of metallic layers wherein one layer of the pair is connected to a voltage supply and the other layer of the pair is connected to a corresponding ground reference.
    Type: Grant
    Filed: October 30, 1995
    Date of Patent: June 24, 1997
    Assignee: VLSI Technology, Inc.
    Inventors: Chin-Ching Huang, Sang S. Lee, Ramachandra A. Rao, Fernand N. Forcier, Jr.
  • Patent number: 5625225
    Abstract: A multi-layered, high performance integrated circuit package is disclosed having a number of design features which increase the performance and manufacturability of the integrated circuit package, and reduce the effects of parasitic noise generated within the package. The metallic layers connecting contact fingers formed on ledges around the periphery of a die cavity area, to their respective package pins are organized such that a ground metallic layer is interposed between each pair of input/output signal metallic layers, and each input/output signal metallic layer is sandwiched between a pair of metallic layers wherein one layer of the pair is connected to a voltage supply and the other layer of the pair is connected to a corresponding ground reference.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: April 29, 1997
    Assignee: VLSI Technology, Inc.
    Inventors: Chin-Ching Huang, Sang S. Lee, Ramachandra A. Rao, Fernand N. Forcier, Jr.
  • Patent number: 5371321
    Abstract: A package assembly for an integrated circuit die includes a base having a cavity formed therein for receiving an integrated circuit die. The base has a ground-reference conductor. A number of bonding wires are each connected between respective die-bonding pads on the integrated circuit die and corresponding bonding pads formed on the base. The lid has an electrically conductive layer formed on it to cover the integrated circuit die in the cavity formed in the base. The electrically conductive layer formed on the lid is positioned in close proximity to some of the plurality of bonding wires. The electrically conductive layer formed on the lid is connected to the ground-reference conductor of the base. This arrangement reduces both the self-inductances of the one or more conductors and the mutual inductance between the one or more conductors. With this arrangement the electrically conductive layer formed on the lid is grounded to reduce interference being radiated from the electrically conductive layer.
    Type: Grant
    Filed: July 22, 1992
    Date of Patent: December 6, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: Ahmad Hamzehdoost, Chin-Ching Huang