Patents by Inventor Chin-Fu Lin

Chin-Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150348971
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Application
    Filed: August 12, 2015
    Publication date: December 3, 2015
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • Publication number: 20150340280
    Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.
    Type: Application
    Filed: August 4, 2015
    Publication date: November 26, 2015
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chun-Ling Lin, Huei-Ru Tsai, Ching-Wei Hsu, Chin-Fu Lin, Hsin-Yu Chen
  • Patent number: 9190292
    Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: November 17, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Hsien Lin, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 9184292
    Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: November 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chun-Yuan Wu, Teng-Chun Tsai, Chih-Chien Liu
  • Patent number: 9184100
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: November 10, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • Patent number: 9166020
    Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: October 20, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chan-Lon Yang, Chi-Mao Hsu, Chun-Yuan Wu, Tzyy-Ming Cheng, Shih-Fang Tzou, Chin-Fu Lin, Hsin-Fu Huang, Min-Chuan Tsai
  • Patent number: 9159831
    Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: October 13, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Liu, Chun-Yuan Wu, Chin-Fu Lin, Chin-Cheng Chien, Chia-Lin Hsu
  • Patent number: 9136170
    Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: September 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chun-Ling Lin, Huei-Ru Tsai, Ching-Wei Hsu, Chin-Fu Lin, Hsin-Yu Chen
  • Publication number: 20150255307
    Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.
    Type: Application
    Filed: May 27, 2015
    Publication date: September 10, 2015
    Inventors: Kun-Hsien LIN, Hsin-Fu HUANG, Chi-Mao HSU, Chin-Fu LIN, Chun-Yuan WU
  • Patent number: 9130032
    Abstract: Provided is a semiconductor device including a substrate, a gate structure, a second dielectric layer and a source/drain region. A first dielectric layer is disposed on the substrate, and the first dielectric layer has a trench therein. The gate structure is disposed on the substrate in the trench and includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench, and includes a TiAl3 phase metal layer. A height of the work function metal layer disposed on a sidewall of the trench is lower than a height of a top surface of the first dielectric layer. The metal layer fills the trench. The second dielectric layer is disposed between the gate structure and the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: September 8, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Fu Huang, Kun-Hsien Lin, Chi-Mao Hsu, Min-Chuan Tsai, Tzung-Ying Lee, Chin-Fu Lin
  • Publication number: 20150249142
    Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.
    Type: Application
    Filed: April 28, 2015
    Publication date: September 3, 2015
    Inventors: Yi-Wei Chen, Nien-Ting Ho, Chien-Chung Huang, Chin-Fu Lin
  • Publication number: 20150206803
    Abstract: A method of forming an inter-level dielectric layer including the following step is provided. Two gate structures are formed on a substrate. A first oxide layer is formed to conformally cover the two gate structures and the substrate. The first oxide layer is etched ex-situ by a high density plasma (HDP) etching process. A second oxide layer is formed in-situ on the first oxide layer and fills a gap between the two gate structures by a high density plasma (HDP) depositing process.
    Type: Application
    Filed: January 19, 2014
    Publication date: July 23, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsin Liu, Tzu-Chin Wu, Jei-Ming Chen, Yu-Ren Wang, Chun-Yuan Wu, Chin-Fu Lin
  • Patent number: 9087782
    Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: July 21, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Hsien Lin, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 9076784
    Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: July 7, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
  • Patent number: 9048254
    Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: June 2, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Wei Chen, Nien-Ting Ho, Chien-Chung Huang, Chin-Fu Lin
  • Publication number: 20150132966
    Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.
    Type: Application
    Filed: December 29, 2014
    Publication date: May 14, 2015
    Inventors: Hung-Lin Shih, Jei-Ming Chen, Chih-Chien Liu, Chin-Fu Lin, Kuan-Hsien Li
  • Patent number: 9024393
    Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: May 5, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ssu-I Fu, Wen-Tai Chiang, Ying-Tsung Chen, Shih-Hung Tsai, Chien-Ting Lin, Chi-Mao Hsu, Chin-Fu Lin
  • Patent number: 9018086
    Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 28, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin, Min-Chuan Tsai, Wei-Yu Chen, Chien-Hao Chen
  • Patent number: 9018087
    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 28, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu
  • Patent number: 8975666
    Abstract: A MOS transistor includes a gate structure on a substrate, and the gate structure includes a wetting layer, a transitional layer and a low resistivity material from bottom to top, wherein the transitional layer has the properties of a work function layer, and the gate structure does not have any work function layers. Moreover, the present invention provides a MOS transistor process forming said MOS transistor.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: March 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ya-Hsueh Hsieh, Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Chi-Yuan Sun, Wei-Yu Chen, Chin-Fu Lin