Patents by Inventor Chin Hsi Lin

Chin Hsi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210224170
    Abstract: A repair method of a memory includes dividing a plurality of general bits into a plurality of first groups and dividing a plurality of redundancy bits into a plurality of second groups. When one of the plurality of first groups has a defective bit, one of the plurality of second groups is selected to replace the first group which has the defective bit. Because the repair method uses a group as a repair unit, a repair circuit is simpler and smaller and a processing speed of the repair circuit is faster.
    Type: Application
    Filed: June 2, 2020
    Publication date: July 22, 2021
    Inventor: CHIN-HSI LIN
  • Publication number: 20210149778
    Abstract: A method of reordering memory bits includes steps of: providing multiple pieces of bit repair data corresponding to memory bits and used to mark whether any one of the memory bits is defective bit; generating selection signals based on multiple pieces of bit repair data; selecting and coupling good memory bits of the memory bits to multiple input/output terminals of a memory, respectively, based on the multiple pieces of bit repair data and the selection signals or based on the selection signals.
    Type: Application
    Filed: February 11, 2020
    Publication date: May 20, 2021
    Inventor: CHIN-HSI LIN
  • Patent number: 7548445
    Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL? to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: June 16, 2009
    Assignee: Macronix International Co., Ltd.
    Inventors: Chin-Hsi Lin, Chi-Ming Weng
  • Patent number: 7453714
    Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL? to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: November 18, 2008
    Assignee: Macronix International Co., Ltd.
    Inventors: Chin-Hsi Lin, Chi-Ming Weng
  • Publication number: 20080225570
    Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL? to further enlarge the voltage difference therebetween after having raised the plate-line /bit-line voltage using the plate-line /bit-line driven method.
    Type: Application
    Filed: May 29, 2008
    Publication date: September 18, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Hsi Lin, Chi-Ming Weng
  • Patent number: 7394678
    Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL? to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: July 1, 2008
    Assignee: Macronix International Co., Ltd.
    Inventors: Chin-Hsi Lin, Chi-Ming Weng
  • Patent number: 7382652
    Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: June 3, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Shiga, Chih-Hung Wang, Chin Hsi Lin
  • Patent number: 7307867
    Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL? to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: December 11, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Chin-Hsi Lin, Chi-Ming Weng
  • Publication number: 20070274119
    Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL? to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.
    Type: Application
    Filed: August 13, 2007
    Publication date: November 29, 2007
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Hsi Lin, Chi-Ming Weng
  • Publication number: 20070247891
    Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL? to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.
    Type: Application
    Filed: June 29, 2007
    Publication date: October 25, 2007
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Hsi Lin, Chi-Ming Weng
  • Patent number: 7233527
    Abstract: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: June 19, 2007
    Assignee: Solid State System Co., Ltd.
    Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
  • Patent number: 7227232
    Abstract: A contactless Mask ROM is described, comprising a plurality of MOS-type memory cells. The memory cells include a plurality of first memory cells and a plurality of second memory cells. The first memory cells have a first channel conductivity so that they are depletion-mode MOS transistors, and the second memory cells have a second channel conductivity so that they are enhanced-mode MOS transistors. In the contactless Mask ROM, a memory cell shares two diffusions with two adjacent memory cells that are aligned with the memory cell along a first direction.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: June 5, 2007
    Assignee: Solid State System Co., Ltd.
    Inventors: Jhyy-Cheng Liou, Chin-Hsi Lin
  • Patent number: 7200038
    Abstract: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: April 3, 2007
    Assignee: Solid State System Co., Ltd.
    Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
  • Patent number: 7161850
    Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: January 9, 2007
    Assignees: Kabushiki Kaisha Toshiba, Solid State System Co., Ltd.
    Inventors: Hitoshi Shiga, Chih-Hung Wang, Chin Hsi Lin
  • Publication number: 20060284234
    Abstract: A nonvolatile memory device, including composite gate structures formed on a substrate in series along a bit line (BL) direction. Each of the composite gate structures has a first storage gate, a second storage gate, and a selection gate between the two storage gates. Each of the composite gate structures is respectively coupled to two world line (WL) connection terminals at the two storage gates and a selection terminal at the selection gate. Each of the storage gates corresponds to a memory bit cell. Multiple doped regions are in the substrate between the composite gate structures. A first selection doped region are formed in the substrate and coupled between a BL connection terminal and a first edge one of the composite gate structure. A second selection doped region is formed in the substrate and coupled between a second edge one of the composite gate structures and a voltage terminal.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Inventors: Tsung-Min Hsieh, Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
  • Publication number: 20060284240
    Abstract: A nonvolatile memory device includes composite gate structures formed on a substrate in series along a bit line direction. The composite gate structure has a first storage gate structure, a second storage gate structure, and a selection gate between the two storage gate structures. Each of the composite gate structures is respectively coupled to two world line connection terminals at the two storage gate structures and a selection terminal at the selection gate. Each of the storage gate structures corresponds to a memory bit cell. Multiple doped regions are in the substrate between the composite gate structures. A first selection doped region are formed in the substrate and coupled between a BL connection terminal and a first edge one of the composite gate structure. A second selection doped region is formed in the substrate and coupled between a second edge one of the composite gate structures and a voltage terminal.
    Type: Application
    Filed: June 22, 2006
    Publication date: December 21, 2006
    Inventors: Tsung-Min Hsieh, Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
  • Patent number: 7119394
    Abstract: A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: October 10, 2006
    Assignee: Solid State System Co., Ltd.
    Inventors: Tsung-Min Hsieh, Jhyy-Cheng Liou, Chien-Hsing Lee, Chin-Hsi Lin
  • Patent number: 7094649
    Abstract: The present invention relates to a multi-level read only memory cell that can store two bits and the fabrication method thereof. The multi-level ROM cell has the storage capacity of two bits and the resultant NAND type ROM memory array can provide four logic states of two bits, thus increasing the data storage capacity.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: August 22, 2006
    Assignee: Solid State System Co., Ltd.
    Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
  • Patent number: 7085160
    Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: August 1, 2006
    Assignees: Kabushiki Kaisha Toshiba, Solid State System Co., Ltd.
    Inventors: Hitoshi Shiga, Chin Hsi Lin
  • Patent number: 7061042
    Abstract: A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: June 13, 2006
    Assignee: Solid State System Co., Ltd.
    Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou