Patents by Inventor Chin-Hsiang Chang
Chin-Hsiang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966162Abstract: A photoresist composition includes a photoactive compound and a polymer. The polymer has a polymer backbone including one or more groups selected from: The polymer backbone includes at least one group selected from B, C-1, or C-2, wherein ALG is an acid labile group, and X is a linking group.Type: GrantFiled: May 22, 2023Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yang Lin, Ching-Yu Chang, Chin-Hsiang Lin
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Publication number: 20240126170Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation, the selectively exposed photoresist layer is developed to form a pattern in the photoresist layer. The photoresist composition includes a polymer including monomer units with photocleaving promoters, wherein the photocleaving promoters are one or more selected from the group consisting of living free radical polymerization chain transfer agents, electron withdrawing groups, bulky two dimensional (2-D) or three dimensional (3-D) organic groups, N-(acyloxy)phthalimides, and electron stimulated radical generators.Type: ApplicationFiled: May 22, 2023Publication date: April 18, 2024Inventors: Chun-Chih HO, Chin-Hsiang Lin, Ching-Yu Chang
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Publication number: 20240118618Abstract: A method of manufacturing a semiconductor device includes forming a first layer having an organic material over a substrate. A second layer is formed over the first layer, wherein the second layer includes a silicon-containing polymer having pendant acid groups or pendant photoacid generator groups. The forming a second layer includes: forming a layer of a composition including a silicon-based polymer and a material containing an acid group or photoacid generator group over the first layer, floating the material containing an acid group or photoacid generator group over the silicon-based polymer, and reacting the material containing an acid group or photoacid generator group with the silicon-based polymer to form an upper second layer including a silicon-based polymer having pendant acid groups or pendant photoacid generator groups overlying a lower second layer comprising the silicon-based polymer. A photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.Type: ApplicationFiled: April 12, 2023Publication date: April 11, 2024Inventors: Chun-Chih HO, Ching-Yu Chang, Chin-Hsiang Lin
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Patent number: 11955338Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.Type: GrantFiled: January 30, 2023Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
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Publication number: 20240103375Abstract: A method of forming a patterned photoresist layer includes the following operations: (i) forming a patterned photoresist on a substrate; (ii) forming a molding layer covering the patterned photoresist; (iii) reflowing the patterned photoresist in the molding layer; and (iv) removing the molding layer from the reflowed patterned photoresist. In some embodiments, the molding layer has a glass transition temperature that is greater than or equal to the glass transition temperature of the patterned photoresist. In yet some embodiments, the molding layer has a glass transition temperature that is 3° C.-30° C. less than the glass transition temperature of the patterned photoresist.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chih HO, Ching-Yu CHANG, Chin-Hsiang LIN
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Publication number: 20240105500Abstract: The present disclosure provides a method for repairing a seam within a conformally deposited material. One or more seam repairing precursor sources may be delivered to seams or voids using a carrier at a super critical fluid phase. At the super critical fluid phase, the carrier has liquid like density and gas like high diffusion capability, therefore capable of delivering the repairing precursor sources to seams or voids under surfaces of a structure. In some embodiments, carbon dioxide or argon may be used as a carrier.Type: ApplicationFiled: February 7, 2023Publication date: March 28, 2024Inventors: Kenichi Sano, Chin-Hsiang Lin, Hsu-Kai Chang, Pinyen Lin
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Publication number: 20240105619Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
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Patent number: 11935894Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.Type: GrantFiled: November 4, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
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Patent number: 11935757Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.Type: GrantFiled: April 10, 2023Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
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Patent number: 11923302Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.Type: GrantFiled: June 30, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
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Patent number: 11923271Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.Type: GrantFiled: July 20, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Noor E. V. Mohamed, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu
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Patent number: 11358252Abstract: A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.Type: GrantFiled: July 18, 2019Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chi Lin, Kun-Tai Wu, You-Hua Chou, Chih-Tsung Lee, Min Hao Hong, Chih-Jen Wu, Chen-Ming Huang, Soon-Kang Huang, Chin-Hsiang Chang, Chih-Yuan Yang
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Publication number: 20190337116Abstract: A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.Type: ApplicationFiled: July 18, 2019Publication date: November 7, 2019Inventors: Shih-Chi LIN, Kun-Tai WU, You-Hua CHOU, Chih-Tsung LEE, Min Hao HONG, Chih-Jen WU, Chen-Ming HUANG, Soon-Kang HUANG, Chin-Hsiang CHANG, Chih-Yuan YANG
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Patent number: 10357867Abstract: A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.Type: GrantFiled: July 18, 2017Date of Patent: July 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chi Lin, Kun-Tai Wu, You-Hua Chou, Chih-Tsung Lee, Min Hao Hong, Chih-Jen Wu, Chen-Ming Huang, Soon-Kang Huang, Chin-Hsiang Chang, Chih-Yuan Yang
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Publication number: 20180227619Abstract: Disclosed is a multimedia server, including a virtual channel management unit, a virtual channel broadcasting unit, and a program on-demand playback unit. The virtual channel management unit associates a number of programs on-demand with a virtual channel, and creates a virtual schedule for the virtual channel. According to the virtual schedule, the virtual channel broadcasting unit provides broadcasting of the virtual channel to a number of nonspecific users. Meanwhile, the program on-demand playback unit, at any time in response to a user instruction selecting a program on-demand, provides the selected program to a user device.Type: ApplicationFiled: December 27, 2017Publication date: August 9, 2018Inventors: Ta-Wei Chien, Yu Chi Chang, Hounien Lin, Chin Hsiang Chang, Chun-Hung Shih
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Publication number: 20170312881Abstract: A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.Type: ApplicationFiled: July 18, 2017Publication date: November 2, 2017Inventors: Shih-Chi LIN, Kun-Tai WU, You-Hua CHOU, Chih-Tsung LEE, Min Hao HONG, Chih-Jen WU, Chen-Ming HUANG, Soon-Kang HUANG, Chin-Hsiang CHANG, Chih-Yuan YANG
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Patent number: 9718164Abstract: A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter.Type: GrantFiled: December 6, 2012Date of Patent: August 1, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chi Lin, Kun-Tai Wu, You-Hua Chou, Chih-Tsung Lee, Min Hao Hong, Chih-Jen Wu, Chen-Ming Huang, Soon-Kang Huang, Chin-Hsiang Chang, Chih-Yuan Yang
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Publication number: 20140162534Abstract: A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter.Type: ApplicationFiled: December 6, 2012Publication date: June 12, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chi LIN, Kun-Tai WU, You-Hua CHOU, Chih-Tsung LEE, Min Hao HONG, Chih-Jen WU, Chen-Ming HUANG, Soon-Kang HUANG, Chin-Hsiang CHANG, Chih-Yuan YANG
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Patent number: 6966318Abstract: A filtering mask includes two filtering bodies with a tube connected therebetween. Two sub-tubes on the tube are inserted in the wearer's nostrils. Each filtering body includes two chambers separated by a separation plate through which through holes are defined. One of the chambers is connected to the tube by a sealing pad which can be opened in one direction, and the other chamber includes a filtering member for filtering air coming from outside. The through holes are controlled by a sealing pad, which can be opened when inhaling and closed when exhaling.Type: GrantFiled: August 17, 2004Date of Patent: November 22, 2005Assignee: Chang Gung UniversityInventors: Sun-Ming Tsuug, Chin-Hsiang Chang
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Patent number: 6336787Abstract: A wafer transfer method using a robot arm for sucking the front-side of the uppermost one of a plurality of wafers stored in a cassette, and for transferring the wafer having a tape adhered to the front-side thereof to a semiconductor tape-peeling device for tape-peeling. Although the wafer warps, the undesired effect that the robot arm crashes any of the wafers can be avoided by using this method.Type: GrantFiled: April 17, 2000Date of Patent: January 8, 2002Assignee: Mosel Vitelic, Inc.Inventors: Chin-hsiang Chang, Yun-liang Ouyang, Chih-shen Yang, Kuei-chang Tsai