Patents by Inventor Chin Kwan Kim

Chin Kwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200135839
    Abstract: A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Kuiwon KANG, Chin-Kwan KIM, Hong Bok WE, Jaehyun YEON
  • Patent number: 10600572
    Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and first and second external electrodes disposed on an external surface of the ceramic body, wherein the dielectric layer contains a barium titanate-based powder particle having a core-shell structure including a core and a shell around the core, the shell having a structure in which titanium is partially substituted with an element having the same oxidation number as that of the titanium in the barium titanate-based powder particle and having an ionic radius different from that of the titanium in the barium titanate-based powder particle, and the shell covers at least 30% of a surface of the core.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Woo Kim, Jong Ho Lee, Min Gi Sin, Hak Kwan Kim, Chin Mo Kim, Chi Hwa Lee, Hong Seok Kim, Woo Sup Kim, Chang Hwa Park
  • Publication number: 20200091062
    Abstract: Certain aspects of the present disclosure provide techniques for forming a cavity with various conductive pad interconnections for receiving an electronic component in an integrated circuit. One example method of fabricating an integrated circuit generally includes forming a conductive metal above a first substrate layer, forming a barrier metal above the conductive metal, disposing at least one second substrate layer above the barrier metal, forming a cavity in the at least one second substrate layer by using a laser to expose the barrier metal and the conductive metal in the cavity, and etching the conductive metal in the form of a conductive pad pattern for coupling the conductive metal to an electronic component.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Inventors: Jaehyun YEON, Hong Bok WE, Chin-Kwan KIM, Kuiwon KANG
  • Patent number: 10580575
    Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and first and second external electrodes disposed on an external surface of the ceramic body, wherein the dielectric layer contains a barium titanate-based powder particle having a core-shell structure including a core and a shell around the core, the shell having a structure in which titanium is partially substituted with an element having the same oxidation number as that of the titanium in the barium titanate-based powder particle and having an ionic radius different from that of the titanium in the barium titanate-based powder particle, and the shell covers at least 30% of a surface of the core.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Woo Kim, Jong Ho Lee, Min Gi Sin, Hak Kwan Kim, Chin Mo Kim, Chi Hwa Lee, Hong Seok Kim, Woo Sup Kim, Chang Hwa Park
  • Patent number: 10510733
    Abstract: A device that includes a printed circuit board (PCB), a package on package (PoP) device, a first encapsulation layer, and a second encapsulation layer. The package on package (PoP) device is coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package having a first electronic package component, a second package coupled to the first package, a gap controller configured to provide a spacing between the first electronic package component and the second package. The gap controller includes a spacer and an adhesive layer. The first encapsulation layer is formed between the first package and the second package. The first encapsulation layer is configured to at least partially encapsulate the gap controller including the spacer and the adhesive layer. The second encapsulation layer is configured to at least partially encapsulates the package on package (PoP) device. The device is configured to provide cellular functionality.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Rajneesh Kumar, Chin-Kwan Kim, Milind Shah
  • Publication number: 20190371652
    Abstract: An interconnect comprises a dielectric, a via formed in the substrate having a first diameter and a second diameter, and a contact pad for aligning the via on the substrate along the second diameter, wherein the contact pad has a width smaller than the second diameter. The contact pad may be line-shaped. The second diameter is approximately 2×-10× bigger than the contact pad width. The contact pad width is approximately 2-15 microns, and the first diameter is approximately 10-60 microns. The substrate may be used for routing input/output signals and design. The via may be performed using photolithography, laser ablation, and/or plasma etching.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 5, 2019
    Inventors: Hong Bok WE, Chin-Kwan KIM, Jaehyun YEON, Kuiwon KANG
  • Publication number: 20190341352
    Abstract: A semiconductor package comprises a substrate, a die mounted on the substrate, and a mold formed over the die and on the substrate, the mold having a top surface and a plurality of tapered side surfaces, wherein the tapered side surfaces provide uniform thickness of an electromagnetic interference (EMI) shielding film.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 7, 2019
    Inventors: Hong Bok WE, Chin-Kwan KIM, Jaehyun YEON, Manuel ALDRETE, David Fraser RAE
  • Patent number: 10431511
    Abstract: In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Shu Zhang, Bonhoon Koo, Manuel Aldrete, Jie Fu, Chin-Kwan Kim, Babak Nejati, Husnu Ahmet Masaracioglu
  • Patent number: 10418178
    Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and first and second external electrodes disposed on an external surface of the ceramic body, wherein the dielectric layer contains a barium titanate-based powder particle having a core-shell structure including a core and a shell around the core, the shell having a structure in which titanium is partially substituted with an element having the same oxidation number as that of the titanium in the barium titanate-based powder particle and having an ionic radius different from that of the titanium in the barium titanate-based powder particle, and the shell covers at least 30% of a surface of the core.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 17, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Woo Kim, Jong Ho Lee, Min Gi Sin, Hak Kwan Kim, Chin Mo Kim, Chi Hwa Lee, Hong Seok Kim, Woo Sup Kim, Chang Hwa Park
  • Patent number: 10410971
    Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: David Fraser Rae, Hong Bok We, Christopher Healy, Chin-Kwan Kim
  • Patent number: 10403707
    Abstract: Examples of this disclosure include a low profile inductor for use in any application with a multi-layer inductor pattern that allows control of optimum H values. Some examples of such an inductive device comprises a plurality of patterned metal coils arranged in a vertical stack, a plurality of conductive vias configured to couple each of the plurality of patterned metal coils together, and a magnetic material disposed between the plurality of patterned metal coils and within each of the plurality of patterned metal coils.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 3, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Chin-Kwan Kim, Joonsuk Park
  • Publication number: 20190172641
    Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and first and second external electrodes disposed on an external surface of the ceramic body, wherein the dielectric layer contains a barium titanate-based powder particle having a core-shell structure including a core and a shell around the core, the shell having a structure in which titanium is partially substituted with an element having the same oxidation number as that of the titanium in the barium titanate-based powder particle and having an ionic radius different from that of the titanium in the barium titanate-based powder particle, and the shell covers at least 30% of a surface of the core.
    Type: Application
    Filed: February 5, 2019
    Publication date: June 6, 2019
    Inventors: Jin Woo KIM, Jong Ho LEE, Min Gi SIN, Hak Kwan KIM, Chin Mo KIM, Chi Hwa LEE, Hong Seok KIM, Woo Sup KIM, Chang Hwa PARK
  • Publication number: 20190081027
    Abstract: A device that includes a printed circuit board (PCB), a package on package (PoP) device, a first encapsulation layer, and a second encapsulation layer. The package on package (PoP) device is coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package having a first electronic package component, a second package coupled to the first package, a gap controller configured to provide a spacing between the first electronic package component and the second package. The gap controller includes a spacer and an adhesive layer. The first encapsulation layer is formed between the first package and the second package. The first encapsulation layer is configured to at least partially encapsulate the gap controller including the spacer and the adhesive layer. The second encapsulation layer is configured to at least partially encapsulates the package on package (PoP) device. The device is configured to provide cellular functionality.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 14, 2019
    Inventors: Rajneesh KUMAR, Chin-Kwan KIM, Milind SHAH
  • Publication number: 20190067221
    Abstract: In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the RFIC (radio frequency integrated circuit). Also, the operations are often limited to a single frequency which limits their utility. In addition, multiple addition build-up layers are required to provide the necessary separation between the antennas and ground layers. To address these issues, it is proposed to provide a device that includes an antenna package, an RFIC package, and an interconnect assembly between the antenna and the RFIC packages. The interconnect assembly may comprise a plurality of interconnects with high aspect ratios and configured to connect one or more antennas of the antenna package with an RFIC of the RFIC package. An air gap may be formed in between the antenna package and the RFIC package for performance improvement.
    Type: Application
    Filed: December 12, 2017
    Publication date: February 28, 2019
    Inventors: Jon Bradley LASITER, Ravindra Vaman SHENOY, Donald William KIDWELL, JR., Mohammad Ali TASSOUDJI, Vladimir APARIN, Seong Heon JEONG, Jeremy DUNWORTH, Alireza MOHAMMADIAN, Mario Francisco VELEZ, Chin-Kwan KIM
  • Publication number: 20190067205
    Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.
    Type: Application
    Filed: August 29, 2017
    Publication date: February 28, 2019
    Inventors: David Fraser RAE, Hong Bok WE, Christopher HEALY, Chin-Kwan KIM
  • Patent number: 10163871
    Abstract: An integrated device that includes a printed circuit board (PCB) and a package on package (PoP) device coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package that includes a first electronic package component (e.g., first die) and a second package coupled to the first package. The integrated device includes a first encapsulation layer formed between the first package and the second package. The integrated device includes a second encapsulation layer that at least partially encapsulates the package on package (PoP) device. The integrated device is configured to provide cellular functionality, wireless fidelity functionality and Bluetooth functionality. In some implementations, the first encapsulation layer is separate from the second encapsulation layer. In some implementations, the second encapsulation layer includes the first encapsulation layer.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Rajneesh Kumar, Chin-Kwan Kim, Milind Shah
  • Publication number: 20180316319
    Abstract: In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 1, 2018
    Inventors: Daeik Daniel KIM, Shu ZHANG, Bonhoon KOO, Manuel ALDRETE, Jie FU, Chin-Kwan KIM, Babak NEJATI, Husnu Ahmet MASARACIOGLU
  • Publication number: 20180286562
    Abstract: Examples of this disclosure include a low profile inductor for use in any application with a multi-layer inductor pattern that allows control of optimum H values. Some examples of such an inductive device comprises a plurality of patterned metal coils arranged in a vertical stack, a plurality of conductive vias configured to couple each of the plurality of patterned metal coils together, and a magnetic material disposed between the plurality of patterned metal coils and within each of the plurality of patterned metal coils.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Hong Bok WE, Chin-Kwan KIM, Joonsuk PARK
  • Patent number: 9947642
    Abstract: A package on package (PoP) device that includes a first package, a second package that is coupled to the first package, and at least one gap controller located between the first package and the second package, where the at least one gap controller is configured to provide a minimum gap between the first package and the second package. The first package includes a first electronic package component (e.g., first die). In some implementations, the at least one gap controller is coupled to the first package, but free of coupling with the second package. The at least one gap controller is located on or about a center of the first package. The at least one gap controller may be located between the first electronic package component (e.g., first die) and the second package. The package on package (PoP) device may include an encapsulation layer between the first package and the second package.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: April 17, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Rajneesh Kumar, Chin-Kwan Kim, Brian Roggeman
  • Patent number: 9806063
    Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: October 31, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chin-Kwan Kim, Rajneesh Kumar, Vladimir Noveski, Jie Fu, Ahmer Raza Syed, Milind Pravin Shah, Omar James Bchir