Patents by Inventor Chin-Ling Huang

Chin-Ling Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11521924
    Abstract: The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Ling Huang
  • Patent number: 11515405
    Abstract: The present application discloses a method for fabricating a semiconductor device with a programmable feature such as anti-fuse The method includes forming a semiconductor fin on a buried insulating layer; forming a dummy gate structure on the semiconductor fin; forming a top insulating layer over the semiconductor fin and covering the dummy gate structure; removing the dummy gate structure and concurrently forming a first trench in the top insulating layer; performing an etch process in the first trench to form a tapered pit separating the semiconductor fin; forming a first insulating layer to completely fill the first trench and the tapered pit; and replacing the semiconductor fin with first conductive blocks.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: November 29, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Ling Huang
  • Publication number: 20220344261
    Abstract: The present disclosure provides a semiconductor device with a copper-manganese liner and a method for forming the semiconductor device. The semiconductor device includes a first electrode and a second electrode disposed in a first dielectric layer. The semiconductor device also includes a first liner separating the first electrode from the first dielectric layer. The semiconductor device further includes a fuse link disposed in the first dielectric layer. The fuse link is disposed between and electrically connected to the first electrode and the second electrode, and the fuse link and the first liner are made of copper-manganese (CuMn).
    Type: Application
    Filed: April 26, 2021
    Publication date: October 27, 2022
    Inventor: CHIN-LING HUANG
  • Publication number: 20220336350
    Abstract: The present disclosure provides a semiconductor device with a copper-manganese liner and a method for preparing the semiconductor device. The semiconductor device includes a first well region and a second well region disposed in a semiconductor substrate. The semiconductor device also includes a first dielectric layer disposed over the semiconductor substrate and covering the first well region and the second well region, and a gate structure disposed over the first dielectric layer and between the first well region and the second well region. The semiconductor device further includes a conductive structure disposed over and separated from the first well region by a portion of the first dielectric layer. The conductive feature includes a barrier layer and a conductive plug disposed over the barrier layer, and the barrier layer is made of copper-manganese (CuMn). The first well region, the conductive structure and the portion of the first dielectric layer form an anti-fuse structure.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Inventor: Chin-Ling HUANG
  • Publication number: 20220285270
    Abstract: The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Inventor: CHIN-LING HUANG
  • Patent number: 11424346
    Abstract: The present application discloses a semiconductor device with a programmable feature such as anti-fuse and a method for fabricating the semiconductor device. The semiconductor device includes a first insulating layer including a peak portion and an upper portion positioned on the peak portion, and first conductive blocks positioned on two sides of the peak portion. A width of the peak portion is gradually decreased toward a direction opposite to the upper portion, and the first conductive blocks are spaced apart by the peak portion.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 23, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Ling Huang
  • Patent number: 11417737
    Abstract: The present disclosure provides a semiconductor structure having a vertical fin with an oxidized sidewall and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate, a top source/drain, a channel fin, a gate structure, a top cathode/anode, and a vertical fin. The substrate has a bottom source/drain and a bottom cathode/anode. The top source/drain is disposed above the bottom source/drain of the substrate, and the channel fin connects the top source/drain to the bottom source/drain of the substrate. The gate structure is disposed on the channel fin. The top cathode/anode is disposed above the bottom cathode/anode of the substrate, and the vertical fin connects the top cathode/anode to the bottom cathode/anode of the substrate, wherein the vertical fin has an oxidized sidewall.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: August 16, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Ling Huang
  • Publication number: 20220165662
    Abstract: The present disclosure provides a semiconductor device with air gaps between adjacent conductive lines and a method for forming the semiconductor device. The semiconductor device with air gaps between adjacent conductive lines and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode.
    Type: Application
    Filed: November 23, 2020
    Publication date: May 26, 2022
    Inventor: CHIN-LING HUANG
  • Publication number: 20220157717
    Abstract: The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure.
    Type: Application
    Filed: November 17, 2020
    Publication date: May 19, 2022
    Inventor: Chin-Ling HUANG
  • Publication number: 20220093769
    Abstract: The present application discloses a method for fabricating a semiconductor device with a programmable feature such as anti-fuse The method includes forming a semiconductor fin on a buried insulating layer; forming a dummy gate structure on the semiconductor fin; forming a top insulating layer over the semiconductor fin and covering the dummy gate structure; removing the dummy gate structure and concurrently forming a first trench in the top insulating layer; performing an etch process in the first trench to form a tapered pit separating the semiconductor fin; forming a first insulating layer to completely fill the first trench and the tapered pit; and replacing the semiconductor fin with first conductive blocks.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 24, 2022
    Inventor: CHIN-LING HUANG
  • Publication number: 20220085178
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure having a vertical fin with an oxidized sidewall. The method of manufacturing the semiconductor structure includes the steps of providing a substrate having a bottom source/drain and a bottom cathode/anode; forming a channel fin on the bottom source/drain of the substrate and a vertical fin on the cathode/anode of the substrate; forming a top source/drain on the channel fin and a top cathode/anode on the vertical fin; forming a gate structure on the channel fin; and forming an oxidized sidewall on the vertical fin.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 17, 2022
    Inventor: CHIN-LING HUANG
  • Publication number: 20220059456
    Abstract: An antifuse structure includes an active area, a gate electrode and a dielectric layer. The gate electrode is over the active area, in which the gate electrode is ring-shaped, and a portion of the gate electrode is overlapped with a portion of the active area in a vertical projection direction, and the portion of the active area has a dopant concentration higher than a dopant concentration of another portion of the active area. The dielectric layer is sandwiched between the portion of the active area and the portion of the gate electrode.
    Type: Application
    Filed: August 18, 2020
    Publication date: February 24, 2022
    Inventors: Chin-Ling HUANG, Yu-Fang CHEN, Chun-Hsien LIN, Chia-Ping LIAO
  • Patent number: 11257756
    Abstract: An antifuse structure includes an active area, a gate electrode and a dielectric layer. The gate electrode is over the active area, in which the gate electrode is ring-shaped, and a portion of the gate electrode is overlapped with a portion of the active area in a vertical projection direction, and the portion of the active area has a dopant concentration higher than a dopant concentration of another portion of the active area. The dielectric layer is sandwiched between the portion of the active area and the portion of the gate electrode.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: February 22, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chin-Ling Huang, Yu-Fang Chen, Chun-Hsien Lin, Chia-Ping Liao
  • Publication number: 20220044747
    Abstract: The present application provides a programmable memory device.
    Type: Application
    Filed: September 30, 2021
    Publication date: February 10, 2022
    Inventor: CHIN-LING HUANG
  • Publication number: 20220045073
    Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 10, 2022
    Inventors: Chin-Ling HUANG, Jhen-Yu TSAI, Cheng-Han YANG, Yi-Ju CHEN
  • Patent number: 11244950
    Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: February 8, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chin-Ling Huang, Jhen-Yu Tsai, Cheng-Han Yang, Yi-Ju Chen
  • Publication number: 20220028987
    Abstract: The present disclosure provides a semiconductor structure having a vertical fin with an oxidized sidewall and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate, a top source/drain, a channel fin, a gate structure, a top cathode/anode, and a vertical fin. The substrate has a bottom source/drain and a bottom cathode/anode. The top source/drain is disposed above the bottom source/drain of the substrate, and the channel fin connects the top source/drain to the bottom source/drain of the substrate. The gate structure is disposed on the channel fin. The top cathode/anode is disposed above the bottom cathode/anode of the substrate, and the vertical fin connects the top cathode/anode to the bottom cathode/anode of the substrate, wherein the vertical fin has an oxidized sidewall.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Inventor: Chin-Ling HUANG
  • Publication number: 20220020687
    Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a peak portion on the substrate, forming a gate insulating layer on the substrate and the peak portion, forming a gate bottom conductive layer on the gate insulating layer, and forming a first doped region in the substrate and adjacent to one end of the gate insulating layer.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 20, 2022
    Inventor: Chin-Ling HUANG
  • Publication number: 20210408264
    Abstract: The present application discloses a semiconductor device with a programmable feature such as anti-fuse and a method for fabricating the semiconductor device. The semiconductor device includes a first insulating layer including a peak portion and an upper portion positioned on the peak portion, and first conductive blocks positioned on two sides of the peak portion. A width of the peak portion is gradually decreased toward a direction opposite to the upper portion, and the first conductive blocks are spaced apart by the peak portion.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventor: CHIN-LING HUANG
  • Publication number: 20210384202
    Abstract: A semiconductor structure includes a substrate, a shallow trench isolation (STI) structure, a first gate structure, a second gate structure, a first contact, and a second gate contact. The substrate has an active region. The STI structure is disposed in the substrate and adjacent to the active region. The first gate structure and the second gate structure is disposed on the active region, wherein a vertical projection region of the first gate structure on the substrate and a vertical projection region of the second gate structure on the substrate are spaced apart from the STI structure. The first contact and the second contact are respectively disposed on the first gate structure and the second gate structure.
    Type: Application
    Filed: June 4, 2020
    Publication date: December 9, 2021
    Inventors: Ting-Cih KANG, Chen CHU, Chin-Ling HUANG, Hsih-Yang CHIU