Abstract: Error correction and detection codes are designed with several properties: the ability to perform error correction and detection operations via syndrome generation in multiple cycles of information delivery from a source such as a set of memory chips; a code structure which is cooperatively designed in terms of the bits-per-chip architecture of a set of memory chips so as to provide enhanced robustness in the face of bus line and chip failures; and a structured parity check matrix which provides circuits which are cheaper, take up less room, and are faster than standard designs.

Abstract: Symbol level multi-cycle error correction and detection coding systems are developed and deployed in computer memory architectures resulting in an increase in robustness in terms of single bus line failures having no effect on the robustness of the coding technique and capabilities. The multi-cycle symbol level error correction techniques of the present invention also provide a mechanism for reducing the pin-out requirements for memory chips and dual in-line memory modules. The resulting ECC circuitry is thus simpler and consumes less real estate.

Abstract: An error correction code for single symbol error correction and double symbol error detection is generated according to a novel modular H-matrix. The H-matrix utilizes a modular design with multiple iterations of a plurality of subsets. In particular, one example of this H-matrix includes a plurality of rows and columns with each of at least one row of the H-matrix comprising, in part, multiple iterations of one subset of the plurality of subsets. The remainder of the rows, comprises, in part, a cyclic permutation of all of the remaining subsets of the plurality of subsets.

Abstract: Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.

Abstract: Uncorrectable errors are detected during the transmission of a data word according to an error correction code. Then, any address faults are identified from among the detected uncorrectable errors. In addition, address faults as well as uncorrectable memory data failures are detected from among the detected uncorrectable errors. Furthermore, address parity bits are not required to be stored to memory.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: The present invention employs an extra array of character history matching storage flip flops wherein the extra set operates in an alternating sequence with the first set depending upon the occurrence of a character mismatch, to ensure that every character received by a data compressing system is treated and considered in the same clock cycle in which it is received. The resultant circuit and method provides a much more speedy and efficient method for compressing data and for preprocessing of data which is to be compressed.

Abstract: In a memory card, identification numbers identifying the memory card are permanently stored in fuse blown registers formed in each of two redrive chips, which function to read out data from memory chips of the memory card and store data in the memory chips of the memory card. Each identification number separately provides a unique identification of the memory card. The identification numbers are each stored with an error correction code by which single bit errors en the identification numbers can be corrected and the occurrence of multiple bit errors in the identification numbers can be detected. Both identification numbers, if valid, are used to identify the memory card and both of the identification numbers, if valid, are stored in association with memory quality events occurring on the memory card, so as to provide a redundant identification of the memory card on which the memory quality events occurred.

Abstract: A single width bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear centimeter, an important consideration in semiconductor manufacturing wherein space on the chips and the wafer is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.

Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.

Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.

Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.

Abstract: A method of detecting errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller, by determining whether the encoding was performed using a first encoding method or a second encoding method, and thereafter decoding the data stream using a logic circuit based on a single parity-check matrix. The entire parity-check matrix is used to decode the data stream if the first encoding method was used, and a subset of the parity-check matrix is used to decode the data stream if the second encoding method was used. Encoding according to the first method allows correction of all single-symbol errors and detection of all double-symbol errors in the data stream, and encoding according to the second method allows correction of all single-bit errors and detection of all double-bit errors in the data stream. The subset matrix may be permuted if the second encoding method was used, to create a permuted matrix further allowing detection of single-symbol errors.

Abstract: A fault tolerant circuit having improved error correction and detection properties takes advantage of two distinct forms of information redundancy: modular redundancy and parity check bit redundancy, in a cooperative fashion. In particular, it is shown that simple majority voting logic circuits, when employed in the subject environment, provide an easily realized mechanism for error correction and error detection. This results in an extremely fault tolerant information system.

Abstract: BCH error correcting code principles are employed in conjunction with normal basis representation of field elements to provide apparatus and method for encoding and decoding binary electrical signals in a way which ensures the ability to correct all double-bit errors and to detect all triple-bit errors. Both the encoder and decoder are designed in a fashion which permits modular implementation so as to make the circuits more compact and easier to layout.

Abstract: Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit position. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.