Patents by Inventor Chin-Szu Lee

Chin-Szu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190088692
    Abstract: An image sensor includes a substrate having a first region and a second region. The image sensor further includes a dielectric layer over the substrate. The image sensor further includes a conductive layer over the dielectric layer, wherein in the first region the conductive layer has a grid shape and in the second region a portion of the conductive layer is concave toward the substrate. The image sensor further includes a protective layer, wherein the protective layer is over the conductive layer in the first region, and over a top surface and along sidewalls of the conductive layer in the second region.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Inventors: Cheng-Yi WU, Chun-Chih LIN, Jian-Shin TSAI, Min-Hui LIN, Wen-Shan CHANG, Yi-Ming LIN, Chao-Ching CHANG, C. H. CHEN, Chin-Szu LEE, Y. T. TSAI
  • Publication number: 20180350601
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Patent number: 10147609
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Publication number: 20180337203
    Abstract: A method of fabricating an image sensor includes depositing a first dielectric layer over a substrate, removing a portion of the first dielectric layer from the substrate to form a trench, depositing a conductive layer over the first dielectric layer and in the trench, forming a protective layer lining a top surface of the conductive layer and sidewalls and a bottom surface of the groove in the conductive layer, and removing a portion of the conductive layer to form a grid structure. A groove corresponding to the trench is formed in the conductive layer.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 22, 2018
    Inventors: Cheng-Yi WU, Chun-Chih LIN, Jian-Shin TSAI, Min-Hui LIN, Wen-Shan CHANG, Yi-Ming LIN, Chao-Ching CHANG, C. H. CHEN, Chin-Szu LEE, Y. T. TSAI
  • Publication number: 20180337128
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Patent number: 10134790
    Abstract: A method of fabricating an image sensor includes depositing a first dielectric layer over a substrate, removing a portion of the first dielectric layer from the substrate to form a trench, depositing a conductive layer over the first dielectric layer and in the trench, forming a protective layer lining a top surface of the conductive layer and sidewalls and a bottom surface of the groove in the conductive layer, and removing a portion of the conductive layer to form a grid structure. A groove corresponding to the trench is formed in the conductive layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Wu, Chun-Chih Lin, Jian-Shin Tsai, Min-Hui Lin, Wen-Shan Chang, Yi-Ming Lin, Chao-Ching Chang, C. H. Chen, Chin-Szu Lee, Y. T. Tsai
  • Patent number: 10050102
    Abstract: Semiconductor devices and manufacturing method thereof are disclosed. The semiconductor device includes a substrate, a device layer, first and second conductive layers, first and second vias, and a MIM capacitor structure. The substrate includes active and passive regions. The device layer is in the active region. The first conductive layer is over the device layer. The second conductive layer is over the first conductive layer, wherein the first conductive layer is disposed between the device layer and the second conductive layer. The first via electrically connects the first and the second conductive layers. The MIM capacitor structure is between the first and the second conductive layers and in the passive region, and includes first and second electrodes and a capacitor dielectric layer therebetween. The capacitor dielectric layer includes Group IIIA-metal oxide or nitride. The second via electrically connects the second conductive layer and one of the first and second electrodes.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Ching Chang, Cheng-Yi Wu, Jian-Shin Tsai, Min-Hui Lin, Yi-Ming Lin, Chin-Szu Lee, Wen-Shan Chang, Yi-Hui Chen
  • Patent number: 10038000
    Abstract: A memory cell includes a selector, a fuse connected to the selector in series, a contact etch stop layer formed on the selector and the fuse, a bit line connected to the fuse, and a word line connected to the selector. The contact etch stop layer includes a high-k dielectric for improving the ability of capturing the electrons, thus the retention time of the memory cell is increased.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: July 31, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Wu, Jian-Shin Tsai, Kuo-Hsien Cheng, Min-Hui Lin, Wei-Li Chen, Chao-Ching Chang, Chung-Yu Hsieh, Chin-Szu Lee
  • Publication number: 20180175196
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Application
    Filed: March 31, 2017
    Publication date: June 21, 2018
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Publication number: 20180096936
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20170358474
    Abstract: A wafer support device includes a susceptor, at least one lift pin, at least one lift pin support base and at least one pad. The susceptor has a bottom surface and a top surface configured to support a wafer. The susceptor has at least one through hole extending between the bottom surface and the top surface. The lift pin is at least partially telescopically received in the through hole of the susceptor. The lift pin support base has at least one coupling feature thereon. The pad is detachably coupled with the coupling feature and supports the lift pin.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Zong-Han HU, Yu-Shan Shih, Chen-Liang Chang, Chin-Szu Lee
  • Publication number: 20170358446
    Abstract: A wafer processing apparatus includes at least one pedestal, at least one ultraviolet (UV) light source, and a window. The pedestal is configured to support a wafer. The UV light source is configured to generate UV radiation to the wafer. The window is present between the pedestal and the UV light source. The UV radiation is capable of passing through the window, and the window is a convex lens, a concave lens, or combinations thereof.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Cheng-Yi WU, Tzu-Shin Chen, Che-Kang Liu, Chi-Shun Wang, Chin-Szu LEE, Chia-Chun HUNG, Li-Hsuan CHU
  • Publication number: 20170250211
    Abstract: Semiconductor image sensor devices and manufacturing method of the same are disclosed. The semiconductor image sensor device includes a substrate, a first pixel and a second pixel, and an isolation structure. The first pixel and second pixel are disposed in the substrate, wherein the first and second pixels are neighboring pixels. The isolation structure is disposed in the substrate and between the first and second pixels, wherein the isolation structure includes a dielectric layer, and the dielectric layer includes silicon oxycarbonitride (SiOCN).
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Chia-Hsing Chou, Yi-Ming Lin, Min-Hui Lin, Chin-Szu Lee
  • Publication number: 20170207298
    Abstract: Semiconductor devices and manufacturing method thereof are disclosed. The semiconductor device includes a substrate, a device layer, first and second conductive layers, first and second vias, and a MIM capacitor structure. The substrate includes active and passive regions. The device layer is in the active region. The first conductive layer is over the device layer. The second conductive layer is over the first conductive layer, wherein the first conductive layer is disposed between the device layer and the second conductive layer. The first via electrically connects the first and the second conductive layers. The MIM capacitor structure is between the first and the second conductive layers and in the passive region, and includes first and second electrodes and a capacitor dielectric layer therebetween. The capacitor dielectric layer includes Group IIIA-metal oxide or nitride. The second via electrically connects the second conductive layer and one of the first and second electrodes.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Chao-Ching Chang, Cheng-Yi Wu, Jian-Shin Tsai, Min-Hui Lin, Yi-Ming Lin, Chin-Szu Lee, Wen-Shan Chang, Yi-Hui Chen
  • Publication number: 20170084620
    Abstract: A memory cell includes a selector, a fuse connected to the selector in series, a contact etch stop layer formed on the selector and the fuse, a bit line connected to the fuse, and a word line connected to the selector. The contact etch stop layer includes a high-k dielectric for improving the ability of capturing the electrons, thus the retention time of the memory cell is increased.
    Type: Application
    Filed: September 17, 2015
    Publication date: March 23, 2017
    Inventors: Cheng-Yi WU, Jian-Shin TSAI, Kuo-Hsien CHENG, Min-Hui LIN, Wei-Li CHEN, Chao-Ching CHANG, Chung-Yu HSIEH, Chin-Szu LEE
  • Publication number: 20090300398
    Abstract: A control structure for a power supply cluster which has a primary power supply and a secondary power supply that are independently linked to AC power and transform the AC power to DC power to supply electric power required by an electronic device in a computer equipment. A switch unit is provided to be linked to the primary power supply and the secondary power supply to get a start signal from the primary power supply and transfer to the secondary power supply. Electric power of the primary power supply also is transferred to the electronic device to present a first power supply status. A judgment unit also is provided to be linked to the primary power supply and the switch unit to get the start signal and defer sending a switch signal to the switch unit so that the electronic device can get electric power from the secondary power supply and present a second power supply status.
    Type: Application
    Filed: May 27, 2008
    Publication date: December 3, 2009
    Inventors: Chin-Szu LEE, Chin-Sung Chen
  • Patent number: 7480811
    Abstract: A power supply system for personal computers aims to provide an additional sub-power supply needed when a personal computer requires a power greater than what can be provided by the original main power supply. This invention provides a sub-power supply in the spare space of the existing chassis of the personal computer without removing the main power supply to augment the power supply. The starting power of the sub-power supply is provided by the main power supply. Hence when the personal computer is in the machine stop condition, only the main power supply consumes electric power. Thereby this invention can preserve a green power.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: January 20, 2009
    Assignee: Topower Computer Industrial Co., Ltd.
    Inventors: Ching-Ling Chou, Michael Chen, Chin-Szu Lee
  • Patent number: 7310250
    Abstract: An output voltage circuit for power supply aims to arrange output DC power according to component voltage and equalizing current. The power supply has a voltage transformation circuit which consists of transformers each has at least one high voltage power and one low voltage power. The high voltage power output from each transformer is coupled in parallel and integrated on the same line to be output to a load at the rear end. Each low voltage power is output through a single line to another load at the rear end. Thus the load of the transformers is reduced and a desired electricity condition can be maintained.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: December 18, 2007
    Assignee: Topower Computer Industrial Co., Ltd
    Inventor: Chin-Szu Lee
  • Publication number: 20070143634
    Abstract: A power supply system for personal computers aims to provide an additional sub-power supply needed when a personal computer requires a power greater than what can be provided by the original main power supply. This invention provides a sub-power supply in the spare space of the existing chassis of the personal computer without removing the main power supply to augment the power supply. The starting power of the sub-power supply is provided by the main power supply. Hence when the personal computer is in the machine stop condition, only the main power supply consumes electric power. Thereby this invention can preserve a green power.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 21, 2007
    Inventors: Ching-Lin Chou, Michael Chen, Chin-Szu Lee
  • Publication number: 20070108841
    Abstract: An external power distribution architecture of a power supply, wherein the existing DC voltages V1, V2 transformed from AC by the power supply are further transformed into the power used by external electronic devices plugged in external power ports. In the present invention, two different levels of DC voltages V1, V2 transformed by the power supply are defined to be voltage sources, and two different levels of target DC voltages V3, V4 output by the external power ports are respectively derived from the DC voltage sources V1, V2 closest to corresponding target voltages V3, V4. Thereby, the present invention can balance power output and reduce transformation power loss.
    Type: Application
    Filed: November 15, 2005
    Publication date: May 17, 2007
    Inventor: Chin-Szu Lee