Abstract: A wafer map recognition method using artificial intelligence includes obtaining wafer maps of a plurality of wafers; performing an unsupervised algorithm on the wafer map of each wafer in the plurality of wafers to generate a feature data set for the corresponding wafer map; and performing a clustering algorithm according to a plurality of feature data sets for the plurality of wafer maps to find a wafer map with a potential defect.

Abstract: An artificial intelligence (AI)-based constrained random verification (CRV) method for a design under test (DUT) includes: receiving a series of constraints; obtaining a limited constraint range according to the series of constraints; generating a series of stimuli according to the limited constraint range; and verifying the DUT by the series of stimuli; wherein at least one of the step of obtaining the limited constraint range according to the series of constraints and the step of generating the series of stimuli according to the limited constraint range employs an AI algorithm.

Abstract: A violation checking method includes generating a violation log report for a design, classifying violation logs in the violation log report into high-risk logs and low-risk logs by a machine learning model, reviewing the high-risk logs, and modifying the design if at least one bug is identified in the high-risk logs.

Abstract: Electronic design automation (EDA) of the present disclosure logically places components of the electronic circuitry onto an electronic design real estate to determine an architectural design placement for the electronic circuitry. The EDA evaluates a metaheuristic algorithm starting with an initial placement of components of the electronic circuitry onto the electronic design real estate to provide multiple possible placements for placing these components of the electronic circuitry onto the electronic design real estate. The EDA utilizes the multiple possible placements of the metaheuristic algorithm to train one or more probabilistic functions of a model-based reinforcement learning (RL) algorithm. The EDA evaluates the model-based RL algorithm utilizing the one or more probabilistic functions to determine the architectural design placement.

Abstract: An artificial intelligence (AI)-based constrained random verification (CRV) method for a design under test (DUT) includes: receiving a series of constraints; obtaining a limited constraint range according to the series of constraints; generating a series of stimuli according to the limited constraint range; and verifying the DUT by the series of stimuli; wherein at least one of the step of obtaining the limited constraint range according to the series of constraints and the step of generating the series of stimuli according to the limited constraint range employs an AI algorithm.

Abstract: A system performs the operations of a neural network agent and a circuit simulator for analog circuit sizing. The system receives an input indicating a specification of an analog circuit and design parameters. The system iteratively searches a design space until a circuit size is found to satisfy the specification and the design parameters. In each iteration, the neural network agent calculates measurement estimates for random sample generated in a trust region, which is a portion of the design space. Based on the measurement estimate, the system identifies a candidate size that optimizes a value metric. The circuit simulator receives the candidate size and generates a simulation measurement. The system calculates updates to weights of the neural network agent and the trust region for a next iteration based on, at least in part, the simulation measurement.