Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: An image sensor structure including a substrate, a light sensing device, a filter structure, and a separation wall is provided. The light sensing device is located in the substrate. The filter structure is located above the light sensing device. The filter structure includes a main filter layer and a first subordinate filter layer. The separation wall surrounds a sidewall of the filter structure. A refractive index of the filter structure is greater than a refractive index of the separation wall.

Abstract: An ultra-hard composite material and a method for manufacturing the same, including mixing a metal carbide powder and a multi-element high-entropy alloy powder to form a mixture, green compacting the mixture, and sintering the mixture to form the ultra-hard composite material. The described multi-element high-entropy alloy consists of five to eleven principal elements, with every principal element occupying a 5 to 35 molar percentage of the alloy.

Abstract: The disclosed is an ultra-hard composite material. The method for manufacturing the ultra-hard composite material includes mixing a metal carbide powder and a multi-element high-entropy alloy powder to form a mixture, green compacting the mixture, and sintering the mixture to form the ultra-hard composite material. The described multi-element high-entropy alloy consists of five to eleven principal elements, with every principal element occupying a 5 to 35 molar percentage of the alloy.

Abstract: A method and system for reducing wafer edge residue following a chemical mechanical polishing operation. A semiconductor wafer can be polished utilizing a chemical mechanical polishing apparatus. Thereafter, an acid etch operation may be performed to remove a residue, such as tungsten (W), collected on the semiconductor wafer as a result of the chemical mechanical polishing operation. A spin etch operation removes residue from the edges of the semiconductor wafer following chemical mechanical polishing of the semiconductor wafer.

Abstract: A mouse pad is provided, including a glass substrate and a surface layer made from a ceramic material and formed on the glass substrate, wherein the ceramic surface layer has many pores with a surface roughness of 1˜20 ?m, such that the ceramic surface layer has a strong resistance to abrasion and deformity. Therefore, the sensitivity of the mouse is maintained and the mouse pad is more durable.

Abstract: A method and system for reducing wafer edge residue following a chemical mechanical polishing operation. A semiconductor wafer can be polished utilizing a chemical mechanical polishing apparatus. Thereafter, an acid etch operation may be performed to remove a residue, such as tungsten (W), collected on the semiconductor wafer as a result of the chemical mechanical polishing operation. A spin etch operation removes residue from the edges of the semiconductor wafer following chemical mechanical polishing of the semiconductor wafer.

Abstract: Liquid leaks from a vessel cause shorts between at least one elongate sensing wire and another conductor when the fluid absorbs into the porous sheath of the sensing wire. The other conductor may comprise a second elongate sensing wire having similar porous sheath or a conductive tray or other conductive collection means. The sensing wire is placed in proximity to the vessel, such as beneath or immediately adjacent. Shorts are detected from the electrical characteristics of a circuit including the sensing wire and location is determined therefrom.

Abstract: A method is disclosed for increasing the surface area of hemispherical-grain polysilicon and for forming a storage-node capacitor plate that can be used in the manufacture of dynamic random access memories (DRAMs). A layer of polycrystalline silicon is deposited on a substrate. This layer is either in-situ doped or doped after it is deposited via implantation or diffusion. Next, an amorphous silicon layer is deposited on top of the polycrystalline silicon layer. Hemispherical-grain (HSG) polysilicon seeds are then grown on the upper surface of the amorphous silicon layer using one of several known techniques. An anneal sequence is then performed in the presence of silane. An initial temperature of about 550° C. is maintained for about 3.5 minutes. At the end of that period, the temperature is ramped at a rate of 2° C. per minutes over a period of about 8 minutes. Upon reaching a temperature of about 568° C., that final temperature is maintained for an additional period of about 6 minutes.

Abstract: An improved hoop support for semiconductor wafers reduces contamination of the wafer during edge beveling operations through the use of support pins that make only line contact with the wafer. The support pins are spaced around the periphery of the hoop and possess a triangular cross section. Two intersecting sides of the pins form an edge that defines the line contact with the wafer. These intersecting sides are preferably inclined relative to the wafer at an angle of between 60 and 80 degrees.

Abstract: A method is disclosed for increasing the surface area of hemispherical-grain polysilicon and for forming a storage-node capacitor plate that can be used in the manufacture of dynamic random access memories (DRAMs). A layer of polycrystalline silicon is deposited on a substrate. This layer is either in-situ doped or doped after it is deposited via implantation or diffusion. Next, an amorphous silicon layer is deposited on top of the polycrystalline silicon layer. Hemispherical-grain (HSG) polysilicon seeds are then grown on the upper surface of the amorphous silicon layer using one of several known techniques. An anneal sequence is then performed in the presence of silane. An initial temperature of about 550° C. is maintained for about 3.5 minutes. At the end of that period, the temperature is ramped at a rate of 2° C. per minutes over a period of about 8 minutes. Upon reaching a temperature of about 568° C., that final temperature is maintained for an additional period of about 6 minutes.

Abstract: An improved hoop support for semiconductor wafers reduces contamination of the wafer during edge beveling operations through the use of support pins that make only line contact with the wafer. The support pins are spaced around the periphery of the hoop and possess a triangular cross section. Two intersecting sides of the pins form an edge that defines the line contact with the wafer. These intersecting sides are preferably inclined relative to the wafer at an angle of between 60 and 80 degrees.

Abstract: A method and system for reducing wafer edge residue following a chemical mechanical polishing operation. A semiconductor wafer can be polished utilizing a chemical mechanical polishing apparatus. Thereafter, an acid etch operation may be performed to remove a residue, such as tungsten (W), collected on the semiconductor wafer as a result of the chemical mechanical polishing operation. A spin etch operation removes residue from the edges of the semiconductor wafer following chemical mechanical polishing of the semiconductor wafer.

Abstract: Liquid leaks from a vessel cause shorts between at least one elongate sensing wire and another conductor when the fluid absorbs into the porous sheath of the sensing wire. The other conductor may comprise a second elongate sensing wire having similar porous sheath or a conductive tray or other conductive collection means. The sensing wire is placed in proximity to the vessel, such as beneath or immediately adjacent. Shorts are detected from the electrical characteristics of a circuit including the sensing wire and location is determined therefrom.

Abstract: A method for forming lining oxide in an opening for a shallow trench isolation and a method for forming a shallow trench isolation incorporating a lining oxide layer are described. In the method for forming lining oxide, a silicon substrate is first provided, followed by a process of forming a pad oxide layer and a silicon nitride mask sequentially on top of the silicon substrate. A trench opening is then patterned and formed in the silicon substrate for the shallow trench isolation. The silicon substrate is then annealed at a temperature of at least 1,000° C. in a furnace in an environment that contains not more than 10 vol. % oxygen. A lining oxide layer is formed in the same furnace used for annealing the structure of the trench opening in the silicon substrate.

Abstract: A stable silicon oxide film for use as a thickness reference is prepared by oxidizing a silicon wafer, having a smooth surface, under carefully controlled conditions thereby growing a film of known thickness and refractive index. This is followed by the deposition of a layer of silicon nitride over said oxide film. The resulting structure may then be used as a reference standard when ellipsometry is routinely employed for measuring the thickness of, for example, gate oxides in field effect devices. It has been found that the thickness of the reference layer remains stable over extended time periods without the need for frequent cleaning.

Abstract: A stable silicon oxide film for use as a thickness reference is prepared by oxidizing a silicon wafer, having a smooth surface, under carefully controlled conditions thereby growing a film of known thickness and refractive index. This is followed by the deposition of a layer of silicon nitride over said oxide film. The resulting structure may then be used as a reference standard when ellipsometry is routinely employed for measuring the thickness of, for example, gate oxides in field effect devices. It has been found that the thickness of the reference layer remains stable over extended time periods without the need for frequent cleaning.

Abstract: A stable silicon oxide film for use as a thickness reference is prepared by oxidizing a silicon wafer, having a smooth surface, under carefully controlled conditions thereby growing a film of known thickness and refractive index. This is followed by the deposition of a layer of silicon nitride over said oxide film. The resulting structure may then be used as a reference standard when ellipsometry is routinely employed for measuring the thickness of, for example, gate oxides in field effect devices. It has been found that the thickness of the reference layer remains stable over extended time periods without the need for frequent cleaning.