Abstract: A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions.

Abstract: High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the drain side of the analog transistors (144, 146) to provide a flat channel doping profile on the drain side. Second pocket regions (200) may be formed in the analog transistors. The flat channel doping profile provides high early voltage and higher gain.

Abstract: A light-sensing diode in a high resistivity semiconductor substrate of a first conductivity type, the substrate having a surface protected by an insulator, comprising

Abstract: An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer.

Abstract: A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions.

Abstract: A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.

Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.

Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.

Abstract: A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.

Abstract: A light-sensing diode having improved efficiency due to an extended junction geometry that provides more than one level of interaction with the light input.

Abstract: An integrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50),(140) and drain regions (55),(145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70),(80) serve as the drain extension regions of the transistors.

Abstract: An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50), (140) and drain regions (55), (145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70), (80) serve as the drain extension regions of the transistor.

Abstract: High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the drain side of the analog transistors (144, 146) to provide a flat channel doping profile on the drain side. Second pocket regions (200) may be formed in the analog transistors. The flat channel doping profile provides high early voltage and higher gain.

Abstract: A light-sensing diode fabricated in a semiconductor substrate having a surface protected by an insulator, comprising a first region of one conductivity type in this substrate, a second region of the opposite conductivity type forming a junction with the first region in the substrate; this junction having a convoluted shape, providing two portions generally parallel to the surface, and a constricted intersection with the surface; and a gate for applying electrical bias across the junction, this gate positioned on the insulator such that it covers all portions of the junction intersection with the surface, thereby creating a gate-controlled photodiode.

Abstract: A light-sensing diode fabricated in a semiconductor substrate having a surface protected by an insulator, comprising a first region of one conductivity type in this substrate, a second region of the opposite conductivity type forming a junction with the first region in the substrate; this junction having a convoluted shape, providing two portions generally parallel to the surface, and a constricted intersection with the surface; and a gate for applying electrical bias across the junction, this gate positioned on the insulator such that it covers all portions of the junction intersection with the surface, thereby creating a gate-controlled photodiode.

Abstract: A light-sensing diode in a high resistivity semiconductor substrate of a first conductivity type, the substrate having a surface protected by an insulator, comprising

Abstract: High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the drain side of the analog transistors (144, 146) to provide a flat channel doping profile on the drain side. Second pocket regions (200) may be formed in the analog transistors. The flat channel doping profile provides high early voltage and higher gain.

Abstract: An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region (well 204 of FIG. 1a) formed in the semiconductor substrate (layer 202 of FIG. 1a), the well region of a second conductivity type opposite that of the first conductivity type; a source region (source region 208 of FIG. 1a) formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region (drain 210 of FIG. 1a) formed in the semiconductor substrate and spaced away from the source region by a channel region (given by length L1+L2), the drain region of the second conductivity type; a conductive gate electrode (layer 218 of FIG. 1a) disposed over the semiconductor substrate and over the channel region; a gate insulating layer (layer 214 of FIG.

Abstract: An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region (18), which permits the n-type region of the Dwell to diffuse under the gate region (18) an sufficient distance to eliminate misalignment effects.

Abstract: High performance digital transistors (140) and analog transistors (144) are formed at the same time. The digital transistors (140) include pocket regions (134) for optimum performance. These pocket regions (134) are partially or completely suppressed from at least the drain side of the analog transistors (144) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors (144).