Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.

Abstract: An image classifying device is provided in the invention. The image classifying device includes a storage device, a calculation circuit and a classifying circuit. The storage device stores information corresponding to a plurality of image classes. The calculation circuit obtains a target image from an image extracting device and obtains the feature vector of the target image. The calculation circuit obtains a first estimation result corresponding to the target image based on the information corresponding to the plurality of image classes and the feature vector and obtains a second estimation result corresponding to the target image based on a reference image, wherein the reference image corresponds to one of the image classes. The classifying circuit adds the target image into one of the image classes based on the first estimation result and the second estimation result.

Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

Abstract: Systems and processes for packing complementary articles of footwear into a container are disclosed. The processes can include utilizing a reusable packing sheet positioned underneath complementary articles of footwear to transfer the complementary articles of footwear into a container. The processes can also include removing the reusable packing sheet from underneath the complementary articles of footwear while the complementary articles of footwear remain positioned in the container. Additional processes can include aligning and sizing complementary articles of footwear for packing in a container.

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

Abstract: A semiconductor device including a cell region which includes components representing a circuit arranged such that a rectangular virtual perimeter is drawable around substantially all of the components and includes first and second virtual side boundaries, the components including: a first conductor which is an intra-cell conductor of a first signal that is internal to the circuit, a first end of the intra-cell conductor being substantially a minimum virtual boundary offset inside the first virtual side boundary; and a second conductor of a second signal of the circuit; a portion of the second conductor having a first end which extends outside the first virtual side boundary by a protrusion length substantially greater than the minimum virtual boundary offset; and a second end of the second conductor being receded inside the second virtual side boundary by a first gap substantially greater than the minimum virtual boundary offset.

Abstract: A method for obtaining a handwriting trajectory is provided. The method includes the following steps: capturing images of handwriting that is written with a writing brush on a piece of paper on a writing platform; obtaining positions where pixels in each of the images are lower than a threshold according to the threshold; and outputting handwriting images according to the positions.

Abstract: Systems and processes for packing complementary articles of footwear into a container are disclosed. The processes can include utilizing a reusable packing sheet positioned underneath complementary articles of footwear to transfer the complementary articles of footwear into a container. The processes can also include removing the reusable packing sheet from underneath the complementary articles of footwear while the complementary articles of footwear remain positioned in the container. Additional processes can include aligning and sizing complementary articles of footwear for packing in a container.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via.

Abstract: The present invention provides a probe apparatus, which comprises a signal transmission device, a probe, and a bottom fixing device. The signal transmission device includes a first transmission part and a second transmission part. An end of the probe is connected electrically below the second transmission part. The bottom fixing device is disposed below the signal transmission device. An end of the bottom fixing device includes a first penetrating hole and a first recess is disposed below the end. The probe passes through the first penetrating hole of the bottom fixing device. The probe is located in the first recess. The bottom fixing device reinforces the mechanical strength of the signal transmission device so that the width of the signal transmission device can be reduced. Thereby, the benefit of high-density arrangement of the probe apparatus can be achieved.

Abstract: Herein disclosed are a method and a test probe for testing an electrical component. The electrical component comprises at least a first electrode and a second electrode. The method comprises the following steps: covering the first electrode with a first conducting flexible layer; driving a first electrode contact to electrically connect a first end of the first electrode contact with the first electrode via the first conducting flexible layer; covering the second electrode with a second conducting flexible layer; and driving a second electrode contact to electrically connect a second end of the second electrode contact with the second electrode via the second conducting flexible layer. The first conducting flexible layer is an anisotropic conductive film.

Abstract: The present invention provides a surge protection module which comprises a carrier board and a probe set. The carrier board is used to carry an electronic component. The probe set is disposed on the carrier board and has a plurality of probes and a short-circuit unit. Each probe is used for contacting the electronic component, and the short-circuit unit is selectively moved to a first position or a second position. When the short-circuit unit is moved to the first position, the short-circuit unit simultaneously contacts and shorts the plurality of probes. When the short-circuit unit is moved to the second position, the short-circuit unit is away from at least one of the plurality of probes.