Patents by Inventor Ching-Chao Huang

Ching-Chao Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220200587
    Abstract: A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.
    Type: Application
    Filed: March 10, 2022
    Publication date: June 23, 2022
    Inventors: Ching-Chao HUANG, Jeremy BUAN, Jingqian TIAN, Tadashi OHSHIDA
  • Publication number: 20220038083
    Abstract: Example implementations described herein are directed to reducing far end cross talk (FEXT), including differential-to-differential far end crosstalk (DDFEXT) or single ended FEXT through generating and applying a delay shifter/inverter that is cascaded onto a target electrical system and shifts the even-mode and odd-mode propagation delay of a target electrical system to be substantially equal, which in turn reduces FEXT in the overall system.
    Type: Application
    Filed: June 25, 2021
    Publication date: February 3, 2022
    Inventors: Ching-Chao HUANG, Jeremy BUAN, Jingqian TIAN, Tadashi OHSHIDA
  • Patent number: 10761175
    Abstract: The present disclosure involves method and apparatus for de-embedding test fixture to extract the electrical behavior of device under test. A calibration board with both “1× open” and “1× short” test structures is fabricated and measured by equipment such as vector network analyzer that produces S parameters. The S parameters of “1× open” and “1× short”, with or without correction factors, are combined to produce the S parameters of equivalent “2× thru” test structure. The S parameters of equivalent “2× thru” are used subsequently to de-embed the test fixture. This present disclosure gives a simpler and more accurate method to create the S parameters of “2× thru” for de-embedding.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 1, 2020
    Assignee: ATAITEC CORPORATION
    Inventor: Ching-Chao Huang
  • Patent number: 10756465
    Abstract: The first terminals have contact arm portions extending in a rectilinear manner in the direction of connector plugging and unplugging; the second terminals have convex contact point portions contactable with an intermediate portion of the contact arm portions in the same direction. When the stub portions of the contact arm portions are divided into a free end side range and a proximal end side range such that the center point of said stub portions in the direction of plugging and unplugging forms a boundary, in the arranged state of the first terminals, impedance at arbitrary locations in the direction of plugging and unplugging within the free end side range is larger than impedance at arbitrary locations in the plugging direction within the proximal end side range.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: August 25, 2020
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventors: Nobuhiro Tamai, Shota Yamada, Clement Kam Lam Luk, Jeremy Buan, Ching-Chao Huang, Tadashi Ohshida
  • Publication number: 20200083622
    Abstract: The first terminals have contact arm portions extending in a rectilinear manner in the direction of connector plugging and unplugging; the second terminals have convex contact point portions contactable with an intermediate portion of the contact arm portions in the same direction. When the stub portions of the contact arm portions are divided into a free end side range and a proximal end side range such that the center point of said stub portions in the direction of plugging and unplugging forms a boundary, in the arranged state of the first terminals, impedance at arbitrary locations in the direction of plugging and unplugging within the free end side range is larger than impedance at arbitrary locations in the plugging direction within the proximal end side range.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 12, 2020
    Inventors: Nobuhiro TAMAI, Shota YAMADA, Clement Kam Lam LUK, Jeremy BUAN, Ching-Chao HUANG, Sunao OSHIDA
  • Patent number: 10249989
    Abstract: Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: April 2, 2019
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventors: Clement Luk, Jeremy Buan, Tadashi Ohshida, Ching-Chao Huang
  • Publication number: 20180261961
    Abstract: Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.
    Type: Application
    Filed: January 24, 2018
    Publication date: September 13, 2018
    Inventors: Clement LUK, Jeremy BUAN, Tadashi OHSHIDA, Ching-Chao HUANG
  • Publication number: 20180238990
    Abstract: The present disclosure involves method and apparatus for de-embedding test fixture to extract the electrical behavior of device under test. A calibration board with both “1× open” and “1× short” test structures is fabricated and measured by equipment such as vector network analyzer that produces S parameters. The S parameters of “1× open” and “1× short”, with or without correction factors, are combined to produce the S parameters of equivalent “2× thru” test structure. The S parameters of equivalent “2× thru” are used subsequently to de-embed the test fixture. This present disclosure gives a simpler and more accurate method to create the S parameters of “2× thru” for de-embedding.
    Type: Application
    Filed: September 7, 2016
    Publication date: August 23, 2018
    Inventor: Ching-Chao HUANG
  • Patent number: 9797977
    Abstract: The present disclosure involves method and apparatus for de-embedding test fixture to extract the electrical behavior of device under test. A calibration board with both “1× open” and “1× short” test structures is fabricated and measured by equipment such as vector network analyzer that produces S parameters. The S parameters of “1× open” and “1× short”, with or without correction factors, are combined to produce the S parameters of equivalent “2× thru” test structure. The S parameters of equivalent “2× thru” are used subsequently to de-embed the test fixture. This present disclosure gives a simpler and more accurate method to create the S parameters of “2× thru” for de-embedding.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 24, 2017
    Assignee: AtaiTec Corporation
    Inventor: Ching-Chao Huang
  • Publication number: 20170192079
    Abstract: The present disclosure involves method and apparatus for de-embedding test fixture to extract the electrical behavior of device under test. A calibration board with both “1× open” and “1× short” test structures is fabricated and measured by equipment such as vector network analyzer that produces S parameters. The S parameters of “1× open” and “1× short”, with or without correction factors, are combined to produce the S parameters of equivalent “2× thru” test structure. The S parameters of equivalent “2× thru” are used subsequently to de-embed the test fixture. This present disclosure gives a simpler and more accurate method to create the S parameters of “2× thru” for de-embedding.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 6, 2017
    Inventor: Ching-Chao HUANG
  • Patent number: 9554455
    Abstract: Systems, methods and apparatuses involving a chip-to-chip communication channel, for reducing Far End Crosstalk (FEXT) through the novel concept of controlling FEXT magnitude and polarity of a component inside a channel, vias or within a connector by implementing broadside and edge couplings to offset cumulative FEXT in a channel, via-connector-via subsystem or a connector. The example implementations described herein can be applied to a chip-to-chip communication channel, mezzanine connectors, backplane connectors and any other connectors requiring via routing, and connector itself that can benefit from FEXT reduction.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: January 24, 2017
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventors: Kunia Aihara, Ching-Chao Huang
  • Publication number: 20150357760
    Abstract: Systems, methods and apparatuses involving a chip-to-chip communication channel, for reducing Far End Crosstalk (FEXT) through the novel concept of controlling FEXT magnitude and polarity of a component inside a channel, vias or within a connector by implementing broadside and edge couplings to offset cumulative FEXT in a channel, via-connector-via subsystem or a connector. The example implementations described herein can be applied to a chip-to-chip communication channel, mezzanine connectors, backplane connectors and any other connectors requiring via routing, and connector itself that can benefit from FEXT reduction.
    Type: Application
    Filed: May 8, 2015
    Publication date: December 10, 2015
    Inventors: Kunia AIHARA, Ching-Chao Huang
  • Patent number: 8357013
    Abstract: The present invention involves connectors for reducing Far-End Crosstalk (FEXT) through the use of novel polarity swapping to negate the cumulative effect of FEXT. Skew adjustment is used to improve the FEXT cancellation from polarity swapping. The polarity reversal location or locations among FEXT sources are optimized to achieve maximum FEXT cancellation. The novelty polarity swapping technique can be applied to a wide variety of connectors, such as mezzanine connectors, backplane connectors, and any other connectors that can benefit from FEXT reduction.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: January 22, 2013
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Tatsuya Arai, Ching-Chao Huang, Clement Kam Lam Luk, Jeremy Buan, Tsutomu Matsuo, Toshiyuki Takada, Masakazu Nagata
  • Publication number: 20100183141
    Abstract: The present invention involves chip-to-chip communication systems for reducing Far-End Crosstalk (FEXT) through the use of novel polarity swapping to negate the cumulative effect of FEXT. Skew adjustment is used to improve the FEXT cancellation from polarity swapping. The polarity reversal location or locations among FEXT sources are optimized to achieve maximum FEXT cancellation. The novelty polarity swapping technique can be applied to a wide variety of systems that can benefit from FEXT reduction.
    Type: Application
    Filed: November 5, 2009
    Publication date: July 22, 2010
    Applicant: Hirose Electric USA Inc.
    Inventors: Tatsuya Arai, Ching-Chao Huang, Clement Kam Lam Luk, Jeremy Buan, Tsutomu Matsuo, Toshiyuki Takada, Masakazu Nagata
  • Publication number: 20100184307
    Abstract: The present invention involves connectors for reducing Far-End Crosstalk (FEXT) through the use of novel polarity swapping to negate the cumulative effect of FEXT. Skew adjustment is used to improve the FEXT cancellation from polarity swapping. The polarity reversal location or locations among FEXT sources are optimized to achieve maximum FEXT cancellation. The novelty polarity swapping technique can be applied to a wide variety of connectors, such as mezzanine connectors, backplane connectors, and any other connectors that can benefit from FEXT reduction.
    Type: Application
    Filed: November 5, 2009
    Publication date: July 22, 2010
    Applicant: Hirose Electric USA Inc.
    Inventors: Tatsuya Arai, Ching-Chao Huang, Clement Kam Lam Luk, Jeremy Buan, Tsutomu Matsuo, Toshiyuki Takada, Masakazu Nagata
  • Patent number: 7737808
    Abstract: A connector has data signal conductors for communicating data signals and voltage reference (power and ground) conductors for the signals' return currents. Voltage reference conductors carrying the same voltage level are coupled together at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals. Decoupling capacitors may alternatively or additionally be inserted between pairs of voltage reference conductors carrying high and low voltage levels at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: June 15, 2010
    Assignee: Hirose Electric
    Inventors: Ching-Chao Huang, Gong-Jong Yeh, Clement Kam Lam Luk, Tatsuya Arai
  • Publication number: 20100045408
    Abstract: A connector has data signal conductors for communicating data signals and voltage reference (power and ground) conductors for the signals' return currents. Voltage reference conductors carrying the same voltage level are coupled together at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals. Decoupling capacitors may alternatively or additionally be inserted between pairs of voltage reference conductors carrying high and low voltage levels at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals.
    Type: Application
    Filed: August 20, 2008
    Publication date: February 25, 2010
    Inventors: Ching-Chao Huang, Gong-Jong Yeh, Clement Kam Lam Luk, Tatsuya Arai
  • Patent number: 7231618
    Abstract: An RLGC library is generated so as to include fringe RLCG functions for 2-D canonical interconnect structures. During parameter extraction for selected interconnect structures of an integrated circuit, printed circuit board, or integrated circuit package design, the RLGC library is used to generate fringe RLGC coefficients which in addition to area RLGC coefficients calculated on-the-fly, are used to generate equivalent RLGC circuits or S-parameters for simulating the interconnect structures.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: June 12, 2007
    Assignee: Optimal Corporation
    Inventors: Ching-Chao Huang, Clement Kam Lam Luk
  • Patent number: 7178125
    Abstract: A method for modeling a triangle meshed interconnect structure using an electrically equivalent three rectangle combination for each triangle in the triangle mesh is described. In the method, a surface of an interconnect structure is meshed with triangles. Three rectangles are then defined for each triangle so that each rectangle shares a different side of the triangle. Rectangle circuit models are determined so that the three rectangles are approximately equivalent electrically to the triangle when coupled together. The interconnect circuit model is then formed by connecting together the rectangle circuit models for all triangles defined on the surface of the interconnect structure.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: February 13, 2007
    Assignee: Optimal Corporation
    Inventor: Ching-Chao Huang
  • Publication number: 20050240883
    Abstract: An RLGC library is generated so as to include fringe RLCG functions for 2-D canonical interconnect structures. During parameter extraction for selected interconnect structures of an integrated circuit, printed circuit board, or integrated circuit package design, the RLGC library is used to generate fringe RLGC coefficients which in addition to area RLGC coefficients calculated on-the-fly, are used to generate equivalent RLGC circuits or S-parameters for simulating the interconnect structures.
    Type: Application
    Filed: April 22, 2004
    Publication date: October 27, 2005
    Inventors: Ching-Chao Huang, Clement Luk