Abstract: Example implementations described herein are directed to reducing far end cross talk (FEXT), including differential-to-differential far end crosstalk (DDFEXT) or single ended FEXT through generating and applying a delay shifter/inverter that is cascaded onto a target electrical system and shifts the even-mode and odd-mode propagation delay of a target electrical system to be substantially equal, which in turn reduces FEXT in the overall system.

Abstract: A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.

Abstract: A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.

Abstract: Example implementations described herein are directed to reducing far end cross talk (FEXT), including differential-to-differential far end crosstalk (DDFEXT) or single ended FEXT through generating and applying a delay shifter/inverter that is cascaded onto a target electrical system and shifts the even-mode and odd-mode propagation delay of a target electrical system to be substantially equal, which in turn reduces FEXT in the overall system.

Abstract: The present disclosure involves method and apparatus for de-embedding test fixture to extract the electrical behavior of device under test. A calibration board with both “1× open” and “1× short” test structures is fabricated and measured by equipment such as vector network analyzer that produces S parameters. The S parameters of “1× open” and “1× short”, with or without correction factors, are combined to produce the S parameters of equivalent “2× thru” test structure. The S parameters of equivalent “2× thru” are used subsequently to de-embed the test fixture. This present disclosure gives a simpler and more accurate method to create the S parameters of “2× thru” for de-embedding.

Abstract: The first terminals have contact arm portions extending in a rectilinear manner in the direction of connector plugging and unplugging; the second terminals have convex contact point portions contactable with an intermediate portion of the contact arm portions in the same direction. When the stub portions of the contact arm portions are divided into a free end side range and a proximal end side range such that the center point of said stub portions in the direction of plugging and unplugging forms a boundary, in the arranged state of the first terminals, impedance at arbitrary locations in the direction of plugging and unplugging within the free end side range is larger than impedance at arbitrary locations in the plugging direction within the proximal end side range.

Abstract: The first terminals have contact arm portions extending in a rectilinear manner in the direction of connector plugging and unplugging; the second terminals have convex contact point portions contactable with an intermediate portion of the contact arm portions in the same direction. When the stub portions of the contact arm portions are divided into a free end side range and a proximal end side range such that the center point of said stub portions in the direction of plugging and unplugging forms a boundary, in the arranged state of the first terminals, impedance at arbitrary locations in the direction of plugging and unplugging within the free end side range is larger than impedance at arbitrary locations in the plugging direction within the proximal end side range.

Abstract: Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.

Abstract: Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.

Abstract: The present disclosure involves method and apparatus for de-embedding test fixture to extract the electrical behavior of device under test. A calibration board with both “1× open” and “1× short” test structures is fabricated and measured by equipment such as vector network analyzer that produces S parameters. The S parameters of “1× open” and “1× short”, with or without correction factors, are combined to produce the S parameters of equivalent “2× thru” test structure. The S parameters of equivalent “2× thru” are used subsequently to de-embed the test fixture. This present disclosure gives a simpler and more accurate method to create the S parameters of “2× thru” for de-embedding.

Abstract: The present disclosure involves method and apparatus for de-embedding test fixture to extract the electrical behavior of device under test. A calibration board with both “1× open” and “1× short” test structures is fabricated and measured by equipment such as vector network analyzer that produces S parameters. The S parameters of “1× open” and “1× short”, with or without correction factors, are combined to produce the S parameters of equivalent “2× thru” test structure. The S parameters of equivalent “2× thru” are used subsequently to de-embed the test fixture. This present disclosure gives a simpler and more accurate method to create the S parameters of “2× thru” for de-embedding.

Abstract: The present disclosure involves method and apparatus for de-embedding test fixture to extract the electrical behavior of device under test. A calibration board with both “1× open” and “1× short” test structures is fabricated and measured by equipment such as vector network analyzer that produces S parameters. The S parameters of “1× open” and “1× short”, with or without correction factors, are combined to produce the S parameters of equivalent “2× thru” test structure. The S parameters of equivalent “2× thru” are used subsequently to de-embed the test fixture. This present disclosure gives a simpler and more accurate method to create the S parameters of “2× thru” for de-embedding.

Abstract: Systems, methods and apparatuses involving a chip-to-chip communication channel, for reducing Far End Crosstalk (FEXT) through the novel concept of controlling FEXT magnitude and polarity of a component inside a channel, vias or within a connector by implementing broadside and edge couplings to offset cumulative FEXT in a channel, via-connector-via subsystem or a connector. The example implementations described herein can be applied to a chip-to-chip communication channel, mezzanine connectors, backplane connectors and any other connectors requiring via routing, and connector itself that can benefit from FEXT reduction.

Abstract: Systems, methods and apparatuses involving a chip-to-chip communication channel, for reducing Far End Crosstalk (FEXT) through the novel concept of controlling FEXT magnitude and polarity of a component inside a channel, vias or within a connector by implementing broadside and edge couplings to offset cumulative FEXT in a channel, via-connector-via subsystem or a connector. The example implementations described herein can be applied to a chip-to-chip communication channel, mezzanine connectors, backplane connectors and any other connectors requiring via routing, and connector itself that can benefit from FEXT reduction.

Abstract: The present invention involves connectors for reducing Far-End Crosstalk (FEXT) through the use of novel polarity swapping to negate the cumulative effect of FEXT. Skew adjustment is used to improve the FEXT cancellation from polarity swapping. The polarity reversal location or locations among FEXT sources are optimized to achieve maximum FEXT cancellation. The novelty polarity swapping technique can be applied to a wide variety of connectors, such as mezzanine connectors, backplane connectors, and any other connectors that can benefit from FEXT reduction.

Abstract: The present invention involves connectors for reducing Far-End Crosstalk (FEXT) through the use of novel polarity swapping to negate the cumulative effect of FEXT. Skew adjustment is used to improve the FEXT cancellation from polarity swapping. The polarity reversal location or locations among FEXT sources are optimized to achieve maximum FEXT cancellation. The novelty polarity swapping technique can be applied to a wide variety of connectors, such as mezzanine connectors, backplane connectors, and any other connectors that can benefit from FEXT reduction.

Abstract: The present invention involves chip-to-chip communication systems for reducing Far-End Crosstalk (FEXT) through the use of novel polarity swapping to negate the cumulative effect of FEXT. Skew adjustment is used to improve the FEXT cancellation from polarity swapping. The polarity reversal location or locations among FEXT sources are optimized to achieve maximum FEXT cancellation. The novelty polarity swapping technique can be applied to a wide variety of systems that can benefit from FEXT reduction.

Abstract: A connector has data signal conductors for communicating data signals and voltage reference (power and ground) conductors for the signals' return currents. Voltage reference conductors carrying the same voltage level are coupled together at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals. Decoupling capacitors may alternatively or additionally be inserted between pairs of voltage reference conductors carrying high and low voltage levels at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals.

Abstract: A connector has data signal conductors for communicating data signals and voltage reference (power and ground) conductors for the signals' return currents. Voltage reference conductors carrying the same voltage level are coupled together at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals. Decoupling capacitors may alternatively or additionally be inserted between pairs of voltage reference conductors carrying high and low voltage levels at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals.

Abstract: An RLGC library is generated so as to include fringe RLCG functions for 2-D canonical interconnect structures. During parameter extraction for selected interconnect structures of an integrated circuit, printed circuit board, or integrated circuit package design, the RLGC library is used to generate fringe RLGC coefficients which in addition to area RLGC coefficients calculated on-the-fly, are used to generate equivalent RLGC circuits or S-parameters for simulating the interconnect structures.