Patents by Inventor Ching-Cheng Lung

Ching-Cheng Lung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10410684
    Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: September 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ting-Hao Chang, Ching-Cheng Lung, Yu-Tse Kuo, Shih-Hao Liang, Chun-Hsien Huang, Shu-Ru Wang, Hsin-Chih Yu
  • Patent number: 10381056
    Abstract: A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 13, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tien-Yu Lu, Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Shou-Sian Chen, Koji Nii, Yuichiro Ishii
  • Patent number: 10366756
    Abstract: A control circuit for a ternary content-addressable memory includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line and a second power supply line. When voltages at the first search line and the second search line match voltages at the first storage unit and the second storage unit, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.
    Type: Grant
    Filed: August 19, 2018
    Date of Patent: July 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
  • Publication number: 20190221238
    Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.
    Type: Application
    Filed: February 21, 2018
    Publication date: July 18, 2019
    Inventors: Chun-Yen Tseng, Ting-Hao Chang, Ching-Cheng Lung, Yu-Tse Kuo, Shih-Hao Liang, Chun-Hsien Huang, Shu-Ru Wang, Hsin-Chih Yu
  • Publication number: 20190206459
    Abstract: A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.
    Type: Application
    Filed: May 29, 2018
    Publication date: July 4, 2019
    Inventors: Tien-Yu Lu, Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Shou-Sian Chen, Koji Nii, Yuichiro Ishii
  • Publication number: 20190206879
    Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.
    Type: Application
    Filed: January 30, 2018
    Publication date: July 4, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Chang-Hung Chen, Shu-Ru Wang, Wei-Chi Lee, Chun-Yen Tseng
  • Publication number: 20190096892
    Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.
    Type: Application
    Filed: October 16, 2018
    Publication date: March 28, 2019
    Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
  • Patent number: 10153287
    Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise an identical first fin structure, the PG2A and the PG2B comprise an identical second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
  • Patent number: 10068909
    Abstract: The present invention provides a layout pattern of a memory device composed of static random access memory (SRAM), comprising four memory units located on a substrate, each memory unit being located in a non-rectangular region, the four non-rectangular regions combine a rectangular region, wherein each memory unit comprises a first inverter comprising a first pull-up transistor (PL1) and a first pull-down transistor (PD1), a second inverter comprises a second pull-up transistor (PL2) and a second pull-down transistor (PD2), an access transistor (PG) and a switching transistor (SW), wherein the source of the PG is coupled to an input terminal of the first inverter and a drain of the SW, a source of the SW is coupled to an output of the second inverter, wherein the PD1, the PD2, the SW, and the PG comprise a first diffusion region, the PL1 and the PL2 comprise a second diffusion region.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Chien-Hung Chen
  • Patent number: 10050044
    Abstract: The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: August 14, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Ping Huang, Chun-Hsien Huang, Yu-Tse Kuo, Ching-Cheng Lung
  • Patent number: 10020049
    Abstract: The present invention provides a six transistor static random-access memory (6T-SRAM) cell, the 6T-SRAM cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 10, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Chih-Wei Tsai
  • Publication number: 20180190344
    Abstract: The present invention provides a six transistor static random-access memory (6T-SRAM) cell, the 6T-SRAM cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.
    Type: Application
    Filed: January 24, 2017
    Publication date: July 5, 2018
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Chih-Wei Tsai
  • Publication number: 20180182766
    Abstract: The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.
    Type: Application
    Filed: February 2, 2017
    Publication date: June 28, 2018
    Inventors: Li-Ping Huang, Chun-Hsien Huang, Yu-Tse Kuo, Ching-Cheng Lung
  • Patent number: 9947673
    Abstract: The present invention provides a semiconductor memory device, includes at least one static random access memory (SRAM) cell, wherein the SRAM cell includes a first pick-up node, and a dielectric oxide SRAM (DOSRAM), disposed in a first dielectric layer and disposed above the SRAM cell when viewed in a cross section view, wherein the DOSRAM includes an oxide semiconductor filed effect transistor (OSFET) and a capacitor, a source of the OSFET is electrically connected to the first pick-up node of the SRAM cell through a via structure, and at least parts of the first dielectric layer are disposed between the source of the OSFET and the via structure, and the capacitor is disposed above the OSFET and electrically connected to a drain of the OSFET when viewed in the cross section view.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: April 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ting-Chia Chang, Shih-Hao Liang, Chun-Yen Tseng, Yu-Tse Kuo, Ching-Cheng Lung, Hung-Chan Lin, Shao-Hui Wu
  • Patent number: 9871048
    Abstract: A memory device includes a pickup area extending along a first direction. The pickup area includes at least one N-pickup structure, distributing along an N-pickup line extending at the first direction. At least one P-pickup structure distributes by alternating with the N-pickup structure at the first direction and interleaves with the N-pickup structure at a second direction. The second direction is perpendicular to the first direction. Dummy pickup structure distributes along the first direction, opposite to the P-pickup structure with respect to the N-pickup line. Further, a cell area is beside the pickup area. The SRAM cells in the cell area form cell rows extending along the second direction. Each SRAM cell covers one N-type well region along the second direction and two P-type well regions along the second direction to sandwich the N-type well region. The N-pickup/P-pickup structures respectively provide first/second substrate voltage to the N-type/P-type well regions.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: January 16, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Li-Ping Huang, Chun-Yen Tseng
  • Patent number: 9859282
    Abstract: A high-density semiconductor structure includes a substrate, a bit line and a first memory unit. The bit line, disposed on the substrate, has a first side and a second side. The first memory unit includes a first transistor, a first capacitor, a second transistor and a second capacitor. The first transistor disposed on the substrate has a first terminal and a second terminal. The first terminal connects the bit line. The first capacitor connects the second terminal of the first transistor. The second transistor disposed on the substrate has a third terminal and a fourth terminal. The third terminal connects the bit line. The second capacitor connects the fourth terminal of the second transistor. The first capacitor and the second capacitor are separated from the bit line in a direction perpendicular to an extending direction of the bit line and located on the first side of the bit line.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Shu-Ru Wang