Patents by Inventor Ching-Chun Liu

Ching-Chun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210020617
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate including a front surface and a back surface; a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, at least a portion of the backside metallization layer forming an inductor structure; and an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate. A method for manufacturing a semiconductor structure is also disclosed.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 21, 2021
    Inventors: MIN-FENG KAO, DUN-NIAN YAUNG, JEN-CHENG LIU, HSING-CHIH LIN, CHING-CHUN WANG
  • Publication number: 20200388706
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Chih-Ming LAI, Ching-Wei TSAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kuo-Cheng CHIANG, Ru-Gun LIU, Wei-Hao WU, Yi-Hsiung LIN, Chia-Hao CHANG, Lei-Chun CHOU
  • Patent number: 10861894
    Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, a plurality of photodiodes is formed from a front-side of a substrate. A plurality of boundary deep trench isolation (BDTI) trenches having a first depth and a plurality of multiple deep trench isolation (MDTI) trenches having a second depth are formed from a back-side of the substrate. A stack of dielectric layers is formed in the BDTI trenches and the MDTI trenches. A plurality of color filters is formed overlying the stack of dielectric layers corresponding to the plurality of photodiodes.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Chuang Wu, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Yen-Ting Chiang, Chun-Yuan Chen, Shen-Hui Hong
  • Patent number: 10823384
    Abstract: A wireless induction lamp includes a transmitter device for emitting wireless electric energy to a lamp receiver device, and the lamp receiver device includes a lamp housing having a transparent part disposed thereon, and a wireless light emitting device is disposed inside the lamp housing and in the transparent part. A first induction coil is disposed around on an outer edge of the wireless light emitting device, and receives the wireless electric energy of the transmitter device, to provide electric energy to the wireless light emitting device to emit light. The wireless induction lamp can wirelessly transmit electrical power to the light emitting element to emit light, so as to reduce disposal of electric wires, and the wireless light emitting device can be turned on/off by just changing a posture angle of the lamp housing to move close to or away from the electromagnetic range of the transmitter device.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: November 3, 2020
    Assignee: DS Power Co., Ltd.
    Inventors: Shen-Jye Shieh, Ching-Yuan Huang, Chih-Hsiung Yu, Li-Han Chen, Ju-Chun Liu, Kai-Yi Chou
  • Publication number: 20200343281
    Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a plurality of pixel regions disposed within a substrate and respectively comprising a photodiode configured to receive radiation that enters the substrate from a back-side. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions surrounding the photodiode. The BDTI structure extends from the back-side of the substrate to a first depth within the substrate. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel regions overlying the photodiode. The MDTI structure extends from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure is a continuous integral unit having a ring shape.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 29, 2020
    Inventors: Wei Chuang Wu, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Yen-Ting Chiang, Chun-Yuan Chen, Shen-Hui Hong
  • Patent number: 10816716
    Abstract: A quantum dot composite material and a manufacturing method and an application thereof are provided. The quantum dot composite material includes an all-inorganic perovskite quantum dot and a modification protection on a surface of the all-inorganic perovskite quantum dot. The all-inorganic perovskite quantum dot has a chemical formula of CsPb(ClaBr1-a-bIb)3, wherein 0?a?1, 0?b?1.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: October 27, 2020
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Hung-Chia Wang, Xue-Jie Zhang, Shin-Ying Lin, An-Cih Tang, Ru-Shi Liu, Tzong-Liang Tsai, Yu-Chun Lee, Ching-Yi Chen, Hung-Chun Tong
  • Publication number: 20200335427
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate, a first metal layer, and a through substrate via (TSV). The semiconductor substrate has an active side. The first metal layer is closest to the active side of the semiconductor substrate, and the first metal layer has a first continuous metal feature. The TSV is extending from the semiconductor substrate to the first continuous metal feature. A width of the TSV at the first metal layer is wider than a width of the first continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Application
    Filed: July 3, 2020
    Publication date: October 22, 2020
    Inventors: MIN-FENG KAO, DUN-NIAN YAUNG, JEN-CHENG LIU, CHING-CHUN WANG, KUAN-CHIEH HUANG, HSING-CHIH LIN, YI-SHIN CHU
  • Patent number: 10811398
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate including a front surface and a back surface; a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, at least a portion of the backside metallization layer forming an inductor structure; and an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate. A method for manufacturing a semiconductor structure is also disclosed.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsing-Chih Lin, Ching-Chun Wang
  • Publication number: 20200327160
    Abstract: A method for video content searching is provided. The method accesses video content and segments the video content into a plurality of frames. The method identifies one or more characteristics for at least a portion of frames of the plurality of frames and determines time frames for each characteristic of the one or more characteristics within the portion of the frames. The method generates frame keywords for the plurality of frames based on the one or more characteristics. The method assigns at least one frame keyword to each time frame within the portion of the frames and generates an index store for the video content. The index store is generated based on the frame keywords and assigning the at least one frame keyword to each frame. The index store includes the frame keywords and time frames assigned to the frame keywords.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 15, 2020
    Inventors: TSAI-HSUAN HSIEH, Peter Wu, Chiwen Chang, Allison Yu, CHING-CHUN LIU, Kate Lin
  • Patent number: 10804155
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • Publication number: 20200312817
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 1, 2020
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 10790194
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • Publication number: 20200303351
    Abstract: A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 10763365
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Ching, Ru-Gun Liu, Wei-Hao Wu, Yi-Hsiung Lin, Chia-Hao Chang, Lei-Chun Chou
  • Patent number: 10747938
    Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan Wu, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
  • Publication number: 20200243580
    Abstract: A method for manufacturing an image sensing device includes forming an interconnection layer over a front surface of a semiconductor substrate. A trench is formed to extend from a back surface of the semiconductor substrate. An etch stop layer is formed along the trench. A buffer layer is formed over the etch stop layer. An etch process is performed for etching the buffer layer. The buffer layer and the etch stop layer include different materials.
    Type: Application
    Filed: April 8, 2020
    Publication date: July 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chuang Wu, Ming-Tsong Wang, Feng-Chi Hung, Ching-Chun Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 10727205
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 10727164
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer in proximity to the active side of the semiconductor substrate, and a through substrate via extending from the semiconductor substrate to a first metal layer of the interconnect layer. The TSV being wider than the continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Ching-Chun Wang, Kuan-Chieh Huang, Hsing-Chih Lin, Yi-Shin Chu
  • Patent number: 10727265
    Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. The photodiode comprises a doped layer with a first doping type and an adjoining region of the substrate with a second doping type that is different than the first doping type. A boundary deep trench isolation (BDTI) structure is disposed between adjacent pixel regions. A multiple deep trench isolation (MDTI) structure overlies the doped layer of the photodiode. The MDTI structure comprises a stack of dielectric layers lining sidewalls of a MDTI trench. A plurality of color filters is disposed at the back-side of the substrate corresponding to the respective photodiode of the plurality of pixel regions and overlying the MDTI structure.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Chuang Wu, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Yen-Ting Chiang, Chun-Yuan Chen, Shen-Hui Hong
  • Publication number: 20200235208
    Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 23, 2020
    Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu