Abstract: A method of manufacturing a semiconductor device includes forming a first bonding layer over a substrate of a first wafer, the first wafer including a first semiconductor die and a second semiconductor die, performing a first dicing process to form two grooves that extend through the first bonding layer, the two grooves being disposed between the first semiconductor die and the second semiconductor die, performing a second dicing process to form a trench that extends through the first bonding layer and partially through the substrate of the first wafer, where the trench is disposed between the two grooves, and thinning a backside of the substrate of the first wafer until the first semiconductor die is singulated from the second semiconductor die.

Abstract: A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.

Abstract: A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.

Abstract: A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.

Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Abstract: A method of forming a semiconductor package includes the following steps. A redistribution layer structure is formed over a first die and a dummy die, wherein the redistribution layer structure is directly electrically connected to the first die. An insulating layer is formed, wherein the insulating layer is disposed opposite to the redistribution layer structure with respect to the first die. At least one thermal through via is formed in the insulating layer.

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.

Abstract: A method including followings is provided. An encapsulated device including a semiconductor die and an insulating encapsulation laterally encapsulating the semiconductor die is provided. An insulating layer is formed over a surface of the encapsulated device. A groove pattern is formed on the insulating layer. A conductive paste is filled in the groove pattern and the conductive paste filled in the groove pattern is cured.

Abstract: A semiconductor device includes a semiconductor die having an insulative layer and a conductive feature in the insulative layer, and a shield in contact with a lateral surface of the conductive feature. In some embodiments, the lateral surface of the conductive feature is aligned with an edge of the insulating material.

Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

Abstract: A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.

Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.

Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.

Abstract: A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.

Abstract: A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface.

Abstract: A method includes forming a metal post over a first dielectric layer, attaching a second dielectric layer over the first dielectric layer, encapsulating a device die, the second dielectric layer, a shielding structure, and the metal post in an encapsulating material, planarizing the encapsulating material to reveal the device die, the shielding structure, and the metal post, and forming an antenna electrically coupling to the device die. The antenna has a portion vertically aligned to a portion of the device die.