Patents by Inventor Ching-Feng Yang

Ching-Feng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190302072
    Abstract: A gas detecting module includes a carrying plate, a sensor, a compartment body and an actuator. The carrying plate has a substrate and a gas opening. The compartment body is divided into a first compartment and a second compartment by a partition plate. The first compartment has an opening. The second compartment has an outlet and accommodates the actuator. The bottom of the compartment body has an accommodation recess receiving the carrying plate, whereby the gas opening is aligned with the outlet, and the sensor packaged on the substrate is disposed within the first compartment through the opening. The partition plate has a notch. The gas detecting module is assembled in a slim-type portable device having a casing. The casing has an inlet aligned with the first compartment. As the actuator is actuated, ambient gas is inhaled into the first compartment, and the sensor detects the gas flowing therethrough.
    Type: Application
    Filed: February 1, 2019
    Publication date: October 3, 2019
    Applicant: Microjet Technology Co., Ltd.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Chi-Chang Yang, Chiu-Lin Lee, Jia-Yu Liao, Ching-Sung Lin, Chih-Kai Chen, Chi-Feng Huang, Yung-Lung Han
  • Publication number: 20190285733
    Abstract: An electronic device includes a base seat, a rotary seat rotatably coupled to the base seat, a drive mechanism for driving the rotary seat to rotate relative to the base seat, a power consumption unit disposed on and co-rotatable with the rotary seat, and a power supply unit. The power supply unit includes a solar panel disposed in the rotary seat and electrically connected to the power consumption unit, and a light emitting module operable to emit light toward the solar panel so that the solar panel transforms light energy into electric energy, which is supplied to the power consumption unit.
    Type: Application
    Filed: September 4, 2018
    Publication date: September 19, 2019
    Applicant: TAIWAN GREEN POINT ENTERPRISES CO., LTD.
    Inventors: Chun-Wei CHEN, Ching-Lung MAO, Chin-Feng YANG
  • Publication number: 20190287819
    Abstract: An integrated fan-out package having a multi-band antenna and a method of forming the same are disclosed. An integrated fan-out package includes a semiconductor die, a molding layer and a plurality of through integrated fan-out vias. The molding layer is aside the semiconductor die. The through integrated fan-out vias are through the molding layer and arranged to form a plurality of dipole antennas. At least one of the plurality of dipole antennas includes two dipole arms each having a transmitting strip and a radiating strip connected to the transmitting part, and the radiating strip has a first part, a second part and a filter part between and in contact with the first part and the second part. The cross-sectional area of the filter part is less than the cross-sectional area of the first part or the second part of the radiating strip.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nan-Chin Chuang, Ching-Feng Yang, Kai-Chiang Wu
  • Publication number: 20190246996
    Abstract: A handheld radiation image detecting system and an operation method thereof are provided. The handheld radiation image detecting system includes a handheld device including a radiation emitter and a first transceiver and a sensing device including a radiation image sensor and a second transceiver. The first transceiver is coupled to the radiation emitter and used for generating a first wave with directionality. The second transceiver is used for receiving the first wave and for generating a second wave with directionality, and the first transceiver is used for receiving the second wave.
    Type: Application
    Filed: June 6, 2018
    Publication date: August 15, 2019
    Inventors: Chi-Kuang Lai, Hsu-Ho Wu, Wei-Hsuan Ho, Ching-Feng Tsai, Che-Yu Chuang, Tsung-Min Yang, Yu-Wei Chen
  • Patent number: 10346576
    Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
  • Publication number: 20190181096
    Abstract: A method includes forming a metal post over a first dielectric layer, attaching a second dielectric layer over the first dielectric layer, encapsulating a device die, the second dielectric layer, a shielding structure, and the metal post in an encapsulating material, planarizing the encapsulating material to reveal the device die, the shielding structure, and the metal post, and forming an antenna electrically coupling to the device die. The antenna has a portion vertically aligned to a portion of the device die.
    Type: Application
    Filed: April 30, 2018
    Publication date: June 13, 2019
    Inventors: Kai-Chiang Wu, Chen-Hua Yu, Ching-Feng Yang, Meng-Tse Chen
  • Patent number: 10312209
    Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao-Wen Shih, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Shih-Wei Liang, Yen-Ping Wang
  • Patent number: 10312112
    Abstract: An integrated fan-out package having a multi-band antenna and a method of forming the same are disclosed. An integrated fan-out package includes a semiconductor die, a molding layer and a plurality of through integrated fan-out vias. The molding layer is aside the semiconductor die. The through integrated fan-out vias are through the molding layer and arranged to form a plurality of dipole antennas. At least one of the plurality of dipole antennas includes two dipole arms each having a transmitting strip and a radiating strip connected to the transmitting part, and the radiating strip has a first part, a second part and a filter part between and in contact with the first part and the second part. The cross-sectional area of the filter part is less than the cross-sectional area of the first part or the second part of the radiating strip.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nan-Chin Chuang, Ching-Feng Yang, Kai-Chiang Wu
  • Publication number: 20190123017
    Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hung-Jen Lin
  • Patent number: 10269588
    Abstract: An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Liang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Chia-Chun Miao, Yen-Ping Wang
  • Publication number: 20190057946
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 10163846
    Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hung-Jen Lin
  • Publication number: 20180366347
    Abstract: An integrated fan-out package having a multi-band antenna and a method of forming the same are disclosed. An integrated fan-out package includes a semiconductor die, a molding layer and a plurality of through integrated fan-out vias. The molding layer is aside the semiconductor die. The through integrated fan-out vias are through the molding layer and arranged to form a plurality of dipole antennas. At least one of the plurality of dipole antennas includes two dipole arms each having a transmitting strip and a radiating strip connected to the transmitting part, and the radiating strip has a first part, a second part and a filter part between and in contact with the first part and the second part. The cross-sectional area of the filter part is less than the cross-sectional area of the first part or the second part of the radiating strip.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nan-Chin Chuang, Ching-Feng Yang, Kai-Chiang Wu
  • Patent number: 10157900
    Abstract: A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Liang, Hsin-Yu Pan, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Chia-Chun Miao
  • Publication number: 20180350752
    Abstract: A semiconductor device includes a semiconductor die, an insulative layer, a plurality of conductive features, a dummy redistribution layer (RDL), and an Electromagnetic Interference (EMI) shield. The insulative layer covers the semiconductor die. The conductive features substantially surround the insulative layer. The dummy RDL is over the insulative layer and electrically disconnected from the semiconductor die. The EMI shield is in contact with the plurality of conductive features and the dummy RDL.
    Type: Application
    Filed: August 6, 2018
    Publication date: December 6, 2018
    Inventors: CHUEI-TANG WANG, VINCENT CHEN, TZU-CHUN TANG, CHEN-HUA YU, CHING-FENG YANG, MING-KAI LIU, YEN-PING WANG, KAI-CHIANG WU, SHOU ZEN CHANG, WEI-TING LIN, CHUN-LIN LU
  • Patent number: 10109605
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20180240723
    Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 23, 2018
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Publication number: 20180233472
    Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: CHAO-WEN SHIH, KAI-CHIANG WU, CHING-FENG YANG, MING-KAI LIU, SHIH-WEI LIANG, YEN-PING WANG
  • Patent number: 10043761
    Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electromagnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chuei-Tang Wang, Vincent Chen, Tzu-Chun Tang, Chen-Hua Yu, Ching-Feng Yang, Ming-Kai Liu, Yen-Ping Wang, Kai-Chiang Wu, Shou Zen Chang, Wei-Ting Lin, Chun-Lin Lu
  • Publication number: 20180211935
    Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.
    Type: Application
    Filed: March 20, 2018
    Publication date: July 26, 2018
    Inventors: MING-KAI LIU, CHUN-LIN LU, KAI-CHIANG WU, SHIH-WEI LIANG, CHING-FENG YANG, YEN-PING WANG, CHIA-CHUN MIAO