Patents by Inventor Ching-Jung Yang

Ching-Jung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210151355
    Abstract: Provided is a semiconductor structure including a pad disposed over and electrically connected to an interconnect structure, wherein the pad has a probe mark, and the probe mark has a concave surface; a protective layer conformally covering the pad and the probe mark; and a bonding structure disposed over the protective layer, wherein the bonding structure includes: a bonding dielectric layer includes a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; a first bonding metal layer including a via plug and a metal feature, wherein the via plug penetrates through the first bonding dielectric material and the protective layer to electrically connect to the pad having the probe mark, the metal feature is located on the via plug and the first bonding dielectric material, and the metal feature is laterally surrounded by the second bonding dielectric material.
    Type: Application
    Filed: December 24, 2020
    Publication date: May 20, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Jie Chen
  • Patent number: 10998293
    Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the methods includes the following steps. A first die is provided, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, and a first pad disposed over and electrically connected to the first interconnect structure. A first bonding dielectric layer is formed over the first die to cover the first die. By using a single damascene process, a first bonding via penetrating the first bonding dielectric layer is formed, to electrically connect the first interconnect structure.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Ching-Jung Yang
  • Patent number: 10985121
    Abstract: Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one end, a metal bump including a top surface and a sidewall, a solder bump on the top surface of the metal bump, a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer, and a polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap. A method for fabricating a semiconductor device is also provided.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chang-Pin Huang, Tung-Liang Shao, Hsien-Ming Tu, Ching-Jung Yang, Yu-Chia Lai
  • Publication number: 20210098423
    Abstract: A package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The through via includes a first barrier layer and a conductive post on the first barrier layer. The dielectric layer is on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a second barrier layer and a conductive layer on the second barrier layer. The conductive layer of the redistribution layer is in contact with the conductive post of the through via.
    Type: Application
    Filed: January 8, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Ming-Fa Chen, Sung-Feng Yeh, Ying-Ju Chen
  • Publication number: 20210090966
    Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.
    Type: Application
    Filed: May 19, 2020
    Publication date: March 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-An Kuo, Ching-Jung Yang, Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Publication number: 20210082849
    Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: TUNG-LIANG SHAO, YU-CHIA LAI, HSIEN-MING TU, CHANG-PIN HUANG, CHING-JUNG YANG
  • Publication number: 20210074681
    Abstract: Provided is a semiconductor package structure including a first die having a first bonding structure thereon, a second die having a second bonding structure thereon, a metal circuit structure, and a first protective structure. The second die is bonded to the first die such that a first bonding dielectric layer of the first bonding structure contacts a second bonding dielectric layer of the second bonding structure. The metal circuit structure is disposed over a top surface of the second die. The first protective structure is disposed within the top surface of the second die, and sandwiched between the metal circuit structure and the second die.
    Type: Application
    Filed: November 18, 2020
    Publication date: March 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Ming-Fa Chen
  • Publication number: 20210043576
    Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first portion includes forming a first patterned conductive pad with a first through hole on a first interconnect structure over a first semiconductor substrate; patterning a dielectric material over the first interconnect structure to form a first patterned dielectric layer with a first opening that passes through a portion of the dielectric material formed inside the first through hole to accessibly expose the first interconnect structure; and forming a conductive material inside the first opening and in contact with the first interconnect structure to form a first conductive connector laterally isolated from the first patterned conductive pad by the first patterned dielectric layer. A singulation process is performed to cut off the first patterned dielectric layer, the first interconnect structure, and the first semiconductor substrate to form a continuous sidewall of a semiconductor structure.
    Type: Application
    Filed: October 22, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20210035907
    Abstract: Integrated circuit devices and method of manufacturing the same are disclosed. An integrated circuit device includes an interconnect structure on a substrate, a passivation layer on the interconnect structure, a plurality of conductive pads on the passivation layer and a through interconnect via (TIV). The interconnect structure includes a plurality of dielectric layers and an interconnect in the plurality of dielectric layers. The plurality of conductive pads includes a first conductive pad electrically connecting the interconnect. The through interconnect via extends through the plurality of dielectric layers and electrically connecting a first conductive layer of the interconnect.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Jie Chen, Ming-Fa Chen
  • Patent number: 10879138
    Abstract: Provided is a semiconductor structure including a substrate, an interconnect structure, a pad, a protective layer, and a bonding structure. The interconnect structure is disposed over the substrate. The pad is disposed over and electrically connected to the interconnect structure. A top surface of the pad has a probe mark and the probe mark has a concave surface. The protective layer conformally covers the top surface of the pad and the probe mark. The bonding structure is disposed over the protective layer. The bonding structure includes a bonding dielectric layer and a first bonding metal layer penetrating the bonding dielectric layer and the protective layer to electrically connect to the pad. A method of manufacturing the semiconductor structure is also provided.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Jie Chen
  • Patent number: 10879198
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao
  • Publication number: 20200395339
    Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the methods includes the following steps. A first die is provided, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, and a first pad disposed over and electrically connected to the first interconnect structure. A first bonding dielectric layer is formed over the first die to cover the first die. By using a single damascene process, a first bonding via penetrating the first bonding dielectric layer is formed, to electrically connect the first interconnect structure.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Ching-Jung Yang
  • Publication number: 20200395254
    Abstract: Provided is a semiconductor structure including a substrate, an interconnect structure, a pad, a protective layer, and a bonding structure. The interconnect structure is disposed over the substrate. The pad is disposed over and electrically connected to the interconnect structure. A top surface of the pad has a probe mark and the probe mark has a concave surface. The protective layer conformally covers the top surface of the pad and the probe mark. The bonding structure is disposed over the protective layer. The bonding structure includes a bonding dielectric layer and a first bonding metal layer penetrating the bonding dielectric layer and the protective layer to electrically connect to the pad. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Jie Chen
  • Patent number: 10867968
    Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a die stack structure, a metal circuit structure, and a protective structure. The die stack structure includes a first die and a second die face-to-face bonded together. The second die includes a plurality of through-substrate vias (TSVs). The metal circuit structure is disposed over a back side of the second die. The protective structure is sandwiched between and in contact with a bottom surface of the metal circuit structure and a top surface of one of the plurality of TSVs of the second die.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Ming-Fa Chen
  • Patent number: 10854564
    Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Liang Shao, Yu-Chia Lai, Hsien-Ming Tu, Chang-Pin Huang, Ching-Jung Yang
  • Publication number: 20200365514
    Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor substrate, a first interconnect structure, a first conductive pad, a first dielectric layer, and a first conductive connector. The first semiconductor substrate includes a plurality of first semiconductor devices therein. The first interconnect structure is disposed over the first semiconductor substrate and electrically coupled to the first semiconductor devices. The first conductive pad is disposed over and electrically coupled to the first interconnect structure. The first dielectric layer covers the first conductive pad and the first interconnect structure, and the first dielectric layer includes a portion extending through the first conductive pad. The first conductive connector is disposed on and electrically coupled to the first interconnect structure, and the first conductive connector extends through the portion of the first dielectric layer.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10840190
    Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor substrate, a first interconnect structure, a first conductive pad, a first dielectric layer, and a first conductive connector. The first semiconductor substrate includes a plurality of first semiconductor devices therein. The first interconnect structure is disposed over the first semiconductor substrate and electrically coupled to the first semiconductor devices. The first conductive pad is disposed over and electrically coupled to the first interconnect structure. The first dielectric layer covers the first conductive pad and the first interconnect structure, and the first dielectric layer includes a portion extending through the first conductive pad. The first conductive connector is disposed on and electrically coupled to the first interconnect structure, and the first conductive connector extends through the portion of the first dielectric layer.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10825804
    Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Pin Huang, Hsien-Ming Tu, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai
  • Publication number: 20200279802
    Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Chia-Wei Tu
  • Patent number: 10658290
    Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Chia-Wei Tu