Abstract: The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.

Abstract: The present invention provides a structure of multi-chips package and Method of the same comprising a substrate with a pre-formed die receiving cavity formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and an elastic dielectric layer filled into a gap between the die and the substrate to absorb thermal mechanical stress; therefore the thickness of the package is reduced and the CTE mismatch of the structure is reduced. The present invention also provides a structure for SIP with higher reliability and lower manufacturing cost. the process is simpler and it is easy to form the multi-chips package than the traditional one. Therefore, the present invention discloses a fan-out WLP with reduced thickness and good CTE matching performance.

Abstract: The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.

Abstract: To pick and place standard first chip size package on a base with a second chip for obtaining an appropriate stacking chip size package than the original chip size package. The package structure has a larger chip size package than the size of the traditional stacking package. Moreover, the terminal pins of the flip chip package may be located on peripheral of LGA package or on array of BGA package.

Abstract: The present invention discloses a structure of wafer level packaging. To use the elastic materials with low k dielectric constant and larger elongation properties as dielectric layers materials used for build up layers of semiconductor device packaging, it can improve the reliability, especially in the board level temperature cycling test. In principle, the elastic dielectric layers can absorb the stress due to CTE (Coefficient of Thermal Expansion) mismatching issue.