Patents by Inventor Ching-Sung Yang
Ching-Sung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11876899Abstract: A random number generator includes a static random number generator, a dynamic entropy source, a counter and a combining circuit. The static random number generator includes an initial random number pool and a static random number pool to output a static random number sequence from one thereof the initial random number pool and the static random number pool. The dynamic entropy source is used to generate a dynamic entropy bit. The counter is used to generate a dynamic random number sequence according to the dynamic entropy bit. The combining circuit is used to output a true random number sequence to a lively random number pool according to the static random number sequence and the dynamic random number sequence. The static random number pool is updated when the lively random number pool is fully updated.Type: GrantFiled: July 22, 2020Date of Patent: January 16, 2024Assignee: PUFsecurity CorporationInventors: Meng-Yi Wu, Chi-Yi Shao, Ching-Sung Yang
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Publication number: 20230333818Abstract: An entropy generator includes a physically unclonable function, a dynamic entropy source and an entropy enhancement engine. The physically unclonable function is used to provide a truly random static entropy. The dynamic entropy source is used to generate a dynamic entropy. The entropy enhancement engine is coupled to the physically unclonable function and the dynamic entropy source, and is used to generate an enhanced entropy according to the truly random static entropy and the dynamic entropy. The expected hamming distance is an expected value of a hamming distance between a truly random static entropy and another truly random static entropy provided by a physically unclonable function (PUF).Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Applicant: PUFsecurity CorporationInventors: Meng-Yi Wu, Chi-Yi Shao, Ching-Sung Yang
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Patent number: 11736286Abstract: A method and a secure boot control circuit for controlling a secure boot of an electronic device. The method is applicable to the secure boot control circuit, and the electronic device includes the secure boot control circuit. The method includes: checking randomness of an output of an entropy source of the secure boot control circuit to generate a check result; utilizing the entropy source to provide a random number sequence; generating a reference code according to the random number sequence; comparing the reference code with an activation code stored in the secure boot control circuit to generate a comparison result; and determining whether to enable at least one function of the electronic device according to at least one of the check result and the comparison result.Type: GrantFiled: December 8, 2021Date of Patent: August 22, 2023Assignee: PUFsecurity CorporationInventors: Meng-Yi Wu, Chia-Cho Wu, Ching-Sung Yang
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Publication number: 20230177173Abstract: An electronic device and a method for performing permission management of a storage device are provided. The storage device includes multiple storage blocks. The electronic device includes a controller and multiple dedicated interfaces, wherein the multiple dedicated interfaces are coupled to multiple ports of the controller. The controller is configured to perform access control of the storage device. The multiple dedicated interfaces correspond to the multiple storage blocks, and each dedicated interface of the multiple dedicated interfaces is configured to provide a dedicated channel for accessing one of the multiple storage blocks corresponding to said each dedicated interface via the controller.Type: ApplicationFiled: October 6, 2022Publication date: June 8, 2023Applicant: PUFsecurity CorporationInventors: Meng-Yi Wu, Chia-Cho Wu, Ching-Sung Yang
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Patent number: 11381394Abstract: An encryption key generating engine includes a random number pool, an entangling string generator, and a control circuit. The random number pool stores a plurality of random bits, and values of the plurality of random bits are generated randomly. The entangling string generator provides an entangling string according to an input key. The control circuit is coupled to the random number pool and the entangling string generator. The control circuit retrieves a sequence of random bits from the plurality of random bits stored in the random number pool according to the input key, receive the entangling string from the entangling string generator, and entangle the entangling string with the sequence of random bits to generate a secret key.Type: GrantFiled: July 16, 2020Date of Patent: July 5, 2022Assignee: PUFsecurity CorporationInventors: Meng-Yi Wu, Ching-Sung Yang
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Publication number: 20220191017Abstract: A method of operating the physically unclonable function (PUF)-based key management system includes upon receiving a key generation request including a parameter, a load balancer dispatching a key generation request including a parameter from an external device according to workloads of a plurality of key management components (KMCs). A KMC having minimum workload among the plurality of KMCs is designated as the key-generation KMC and the key generation request is dispatched thereto, and remaining KMCs of the plurality of KMCs are designated as backup KMCs. The method further includes the key-generation KMC generating a key according to the parameter and a first PUF sequence, transmitting the key and an identifier associated therewith to the backup KMC via a backup channel, and the backup KMC generating a wrapped key according to the key and a second PUF sequence.Type: ApplicationFiled: December 3, 2021Publication date: June 16, 2022Applicant: PUFsecurity CorporationInventors: Yung-Hsiang Liu, Meng-Yi Wu, Ching-Sung Yang
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Publication number: 20220188422Abstract: A method and a secure boot control circuit for controlling a secure boot of an electronic device. The method is applicable to the secure boot control circuit, and the electronic device includes the secure boot control circuit. The method includes: checking randomness of an output of an entropy source of the secure boot control circuit to generate a check result; utilizing the entropy source to provide a random number sequence; generating a reference code according to the random number sequence; comparing the reference code with an activation code stored in the secure boot control circuit to generate a comparison result; and determining whether to enable at least one function of the electronic device according to at least one of the check result and the comparison result.Type: ApplicationFiled: December 8, 2021Publication date: June 16, 2022Applicant: PUFsecurity CorporationInventors: Meng-Yi Wu, Chia-Cho Wu, Ching-Sung Yang
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Publication number: 20210051010Abstract: A memory device includes a physically unclonable function (PUF) unit, a controller and a memory array. The PUF unit is used to provide a random bit pool. The controller is coupled to the PUF unit and is used to extract a random bit sequence from the random bit pool. The controller includes a masking engine. The masking engine is used to perform a key derivation function to stretch the extracted random bit sequence and to mask an input signal. The memory array is coupled to the masking engine and is used to store according to the masked input signal.Type: ApplicationFiled: June 9, 2020Publication date: February 18, 2021Inventors: Ching-Sung Yang, Meng-Yi Wu, Chia-Cho Wu
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Publication number: 20210028935Abstract: An encryption key generating engine includes a random number pool, an entangling string generator, and a control circuit. The random number pool stores a plurality of random bits, and values of the plurality of random bits are generated randomly. The entangling string generator provides an entangling string according to an input key. The control circuit is coupled to the random number pool and the entangling string generator. The control circuit retrieves a sequence of random bits from the plurality of random bits stored in the random number pool according to the input key, receive the entangling string from the entangling string generator, and entangle the entangling string with the sequence of random bits to generate a secret key.Type: ApplicationFiled: July 16, 2020Publication date: January 28, 2021Inventors: Meng-Yi Wu, Ching-Sung Yang
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Publication number: 20210026602Abstract: An entropy generator includes a static entropy source, a dynamic entropy source and an entropy enhancement engine. The static entropy source is used to provide a truly random static entropy. The dynamic entropy source is used to generate a dynamic entropy. The entropy enhancement engine is coupled to the static entropy source and the dynamic entropy source, and is used to generate an enhanced entropy according to the truly random static entropy and the dynamic entropy.Type: ApplicationFiled: April 27, 2020Publication date: January 28, 2021Inventors: Meng-Yi Wu, Chi-Yi Shao, Ching-Sung Yang
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Publication number: 20210026603Abstract: A random number generator includes a static random number generator, a dynamic entropy source, a counter and a combining circuit. The static random number generator includes an initial random number pool and a static random number pool to output a static random number sequence from one thereof the initial random number pool and the static random number pool. The dynamic entropy source is used to generate a dynamic entropy bit. The counter is used to generate a dynamic random number sequence according to the dynamic entropy bit. The combining circuit is used to output a true random number sequence to a lively random number pool according to the static random number sequence and the dynamic random number sequence. The static random number pool is updated when the lively random number pool is fully updated.Type: ApplicationFiled: July 22, 2020Publication date: January 28, 2021Inventors: Meng-Yi Wu, Chi-Yi Shao, Ching-Sung Yang
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Patent number: 10685728Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.Type: GrantFiled: November 23, 2018Date of Patent: June 16, 2020Assignee: eMemory Technology Inc.Inventors: Wei-Zhe Wong, Ching-Sung Yang, Ching-Hsiang Hsu
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Patent number: 10476680Abstract: An electronic device having anti-cloning function includes a first critical integrated circuit, which further includes a first security function block configured to authenticate an identity of a second critical integrated circuit in communication with the first critical integrated circuit, wherein the first security function block authenticates the identity of the second critical integrated circuit according to a chip identity of the second critical integrated circuit created using a non-volatile memory (NVM) physically unclonable function (PUF).Type: GrantFiled: February 2, 2017Date of Patent: November 12, 2019Assignee: eMemory Technology Inc.Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Publication number: 20190096497Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.Type: ApplicationFiled: November 23, 2018Publication date: March 28, 2019Applicant: eMemory Technology Inc.Inventors: Wei-Zhe Wong, Ching-Sung Yang, Ching-Hsiang Hsu
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Publication number: 20190096496Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.Type: ApplicationFiled: November 23, 2018Publication date: March 28, 2019Applicant: eMemory Technology Inc.Inventors: Wei-Zhe Wong, Ching-Sung Yang, Ching-Hsiang Hsu
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Patent number: 10181357Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.Type: GrantFiled: May 27, 2016Date of Patent: January 15, 2019Assignee: eMemory Technology Inc.Inventors: Wei-Zhe Wong, Ching-Sung Yang, Ching-Hsiang Hsu
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Patent number: 10020268Abstract: A random number generator device has at least at least a memory unit, a voltage generator, and a control circuit. Each memory unit has two memory cells, one of the two memory cells is coupled to a bias line and a first bit line, and another of the two memory cells is coupled to the bias line and a second bit line. The voltage generator provides the two memory cells a bias voltage, a first bit line voltage and a second bit line voltage via the bias line, the first bit line and the second bit line respectively. The control circuit shorts the first bit line and the second bit line to program the two memory cells simultaneously during a programming period and generates a random number bit according the statuses of the two memory cells during a reading period.Type: GrantFiled: April 13, 2017Date of Patent: July 10, 2018Assignee: eMemory Technology Inc.Inventors: Wei-Zhe Wong, Ching-Hsiang Hsu, Ching-Sung Yang
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Publication number: 20170301406Abstract: A random number generator device has at least at least a memory unit, a voltage generator, and a control circuit. Each memory unit has two memory cells, one of the two memory cells is coupled to a bias line and a first bit line, and another of the two memory cells is coupled to the bias line and a second bit line. The voltage generator provides the two memory cells a bias voltage, a first bit line voltage and a second bit line voltage via the bias line, the first bit line and the second bit line respectively. The control circuit shorts the first bit line and the second bit line to program the two memory cells simultaneously during a programming period and generates a random number bit according the statuses of the two memory cells during a reading period.Type: ApplicationFiled: April 13, 2017Publication date: October 19, 2017Inventors: Wei-Zhe Wong, Ching-Hsiang Hsu, Ching-Sung Yang
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Publication number: 20170222817Abstract: An electronic device having anti-cloning function includes a first critical integrated circuit, which further includes a first security function block configured to authenticate an identity of a second critical integrated circuit in communication with the first critical integrated circuit, wherein the first security function block authenticates the identity of the second critical integrated circuit according to a chip identity of the second critical integrated circuit created using a non-volatile memory (NVM) physically unclonable function (PUF).Type: ApplicationFiled: February 2, 2017Publication date: August 3, 2017Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Patent number: 9638549Abstract: An integrated capacitance sensing module includes a silicon substrate, a first and a second and a third interlayer dielectric layers, plural conducting layers, a shielding layer, a lower and a upper sensing electrode layers, a protective coating layer. An embedded memory and a sensing circuit are constructed in the silicon substrate. The first interlayer dielectric layer covers the silicon substrate. The plural conducting layers are formed over the first interlayer dielectric layer. The shielding layer is formed over the plural conducting layers. The second interlayer dielectric layer covers the shielding layer. The lower sensing electrode layer is formed over the second interlayer dielectric layer. The third interlayer dielectric layer is formed over the lower sensing electrode layer. The upper sensing electrode layer is formed over the third interlayer dielectric layer. The protective coating layer covers the upper sensing electrode layer.Type: GrantFiled: June 3, 2015Date of Patent: May 2, 2017Assignee: EMEMORY TECHNOLOGY INC.Inventors: Wei-Ren Chen, Wen-Hao Lee, Hsin-Chou Liu, Ching-Sung Yang