Abstract: The TFT structure formed in accordance with this invention includes a TFT body that has channel plug end sidewalls separated by a distance equal to or less than the width of the source/drain address lines and such that no residual doped semiconductor material adheres to the sidewalls. Similarly, the intrinsic semiconductor material layer is shaped such that no residual doped semiconductor material adheres to the sidewalls of the intrinsic semiconductor material layer underlying the channel plug ends.

Abstract: A collimator for use in an imaging system with a radiation point source is formed from a plurality of collimator plates stacked together. Passages in each collimator plate in conjunction with the respective passages in adjoining plates form a plurality of channels through the collimator. The channel longitudinal axes are aligned with selected orientation angles that correspond to the direct beam path from the radiation source to the radiation detectors. The collimator plates are made up of patterned sheets of radiation absorbent material or alternatively comprise patterned photosensitive material substrates coated with a radiation absorbent material. The cross-sectional shape of each channel corresponds to the cross-sectional shape of the radiation detecting area of the detector element adjoining the channel.

Abstract: A collimator for use in an imaging system with a radiation point source has a plurality of channels formed therein along longitudinal axes aligned with selected orientation angles that correspond to the direct beam path from the radiation source to the radiation detectors. The collimator comprises a photosensitive material coated with a radiation absorbent material. The cross-sectional shape of the channels corresponds to the cross-sectional shape of the radiation detecting area of the detector element adjoining the channel, and the sidewalls of the channel are smooth along their length.

Abstract: A radiation imager includes a photodetector array having topographically patterned surface features, which include support islands disposed over the active portion of one or more photodetectors in the photodetector array. A structured scintillator array having individual columnar scintillator elements is disposed in fixed relation to the photodetector array so that the individual scintillator elements are disposed on scintillator support islands. A barrier layer is disposed between the support islands and the photodetector array to minimize chemical interactions between the material forming the support island and the underlying photodetector array during the fabrication process. After the support islands have been patterned, the scintillator elements are grown by selectively depositing scintillator material on the support islands.

Abstract: Positive control over the length of the overlap between the gate electrode and the source and drain electrodes in a thin film transistor is provided by a gate conductor layer comprising two different conductors having differing etching characteristics. As part of the gate conductor pattern definition process, both gate conductors are etched to expose the underlying material and the upper gate conductor layer is etched back to expose the first gate conductor layer in accordance with the desired overlap between the gate electrode and the source and drain electrodes. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the second gate conductor layer using a planarization and non-selective etch method.

Abstract: A thin film transistor includes a two-layer gate metallization comprising a relatively thin first layer of a first conductor and a relatively thick second layer of a second conductor with the second conductor being capable of being etched with an etchant that produces substantially no etching of the first conductor layer. During device fabrication, the thick gate metallization layer (second conductor) is selectively etched until all of that material is removed in the openings in the mask. The thin lower layer (first conductor) is then etched with a minimum of etching into the substrate. The gate dielectric and subsequent layers deposited over this gate metallization have high integrity and highly reliable continuity because of the sloped nature of the gate metallization sidewalls, and because of the shallow gate metallization topography due to minimization of substrate etching during gate metallization patterning.

Abstract: Improved buried oxide (BOX) field isolation in a silicon structure which has a trench with a curved side wall is achieved by employing reactive ion etching or local oxidation of silicon to produce the curved side wall. Electric field enhancement which normally occurs at sharp corners in silicon structures employing conventional buried oxide field isolation is minimized by the curved side wall. The buried oxide field isolation in the silicon structure is provided by chemical vapor deposited SiO.sub.2 atop thermally produced SiO.sub.2 in the field region.

Abstract: A method for forming a field oxide isolation region for a field effect transistor for use in integrated circuit chip devices includes process steps which preserve planarity while at the same time providing an increased degree of radiation hardness. The bird's beak region of the device is provided with both thermally grown and deposited oxide layers in a planarity preserving process.

Abstract: Improved buried oxide (BOX) field isolation in a silicon structure which has a trench with a curved side wall is achieved by employing reactive ion etching or local oxidation of silicon to produce the curved side wall. Electric field enhancement which normally occurs at sharp corners in silicon structures employing conventional buried oxide field isolation is minimized by the curved side wall. The buried oxide field isolation in the silicon structure is provided by chemical vapor deposited SiO.sub.2 atop thermally produced SiO.sub.2 in the field region.

Abstract: Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a graded, buried spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur.

Abstract: An improved method and apparatus for reducing edge field enhancement in semiconductor devices such as metal-insulator-semiconductor devices is disclosed. The method comprises the step of biasing a buffer gate which overlies an insulation layer and an area of a substrate in which it is desired to reduce the edge field enhancement at a voltage exceeding the flatband voltage so that a buffered zone is created in the substrate. The apparatus consists of a substrate, a plurality of insulating layers overlying the substrate, at least one gate electrode formed on one of the insulating layers and a buffer gate formed on a second of the insulating layers. When the gate electrode is biased so that a potential well is formed in the substrate, the buffer gate is simultaneously biased so that a buffered zone which adjoins the potential well is formed.

Abstract: Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a surface spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur. Additionally, a surface implant is performed to improve any gate control that may be lost as a result of the buried channel so as to mitigate any degradition of the current-voltage characteristics of the device.

Abstract: Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a graded, buried spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur.

Abstract: Each unit cell of a Schottky barrier photodiode imaging array comprises a Schottky metal electrode formed on a silicon substrate. The Schottky electrode is reverse biased with a pulse for beginning a sensing interval, following which the change in charge on the electrode is related to the quantity of incident infrared radiation. For X-Y addressable readout, a row electrode and a column electrode are capacitively coupled to each Schottky electrode and connected to row and column address lines. For low overlap capacitance and low stray capacitance, the row and column electrodes are concentric within each cell and coplanar above the Schottky electrode. Over the row and column electrodes is an address line insulating layer, and sets of row and column address lines are coplanar over this layer.

Abstract: Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a surface spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur. Additionally, a surface implant is performed to improve any gate control that may be lost as a result of the buried channel so as to mitigate any degradation of the current-voltage characteristics of the device.

Abstract: A method of etching a desired pattern in a thin film of chromium deposited on a substrate is described. A layer of a masking material which is etch-resistant is formed on the film of chromium and provided with the desired pattern. Portions of the thin film of chromium uncovered by the patterned layer of etch-resistant material are covered with a thin layer of aluminum having a multiplicity of holes. The substrate including the layer of aluminum in contact with thin film of chromium is immersed in a dilute hydrochloric acid solution whereby the layer of aluminum and the portion of the thin film of chromium in contact therewith are dissolved thereby providing the desired pattern in the thin film of chromium.

Abstract: An antitheft device comprising a timing circuit and preferably a rotary lock switch operated by a key will interrupt an utilization apparatus such as the ignition circuit of an automobile and sound an alarm unless the lock switch can be unlocked from a first locking position to a second locking position, and unless the lock switch can be unlocked from the second locking position to a third locking position neither earlier than a first predetermined time nor later than a second predetermined time after the lock switch is unlocked to the second locking position.