Patents by Inventor Ching-Yu Hung

Ching-Yu Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080117980
    Abstract: Deblock filtering for Microsoft WMV video decoders partitions the computation so that the deblock filtering operations can be performed on horizontal or vertical stripes or in one pass on oversized macroblocks.
    Type: Application
    Filed: November 16, 2006
    Publication date: May 22, 2008
    Inventors: Ching-Yu Hung, Ngai-Man Cheung
  • Patent number: 7362362
    Abstract: A programmable data reformatter reorders output from an image sensor to yield various formats. The reformatting applies to reduced resolution output from large image sensors as in digital cameras operating in video mode, and converts an irregular video mode output to a standard format, such as Bayer pattern, for image processing.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: April 22, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Deependra Talla, Clay Dunsmore, Ching-Yu Hung
  • Patent number: 7333141
    Abstract: Polyphase filtering, such as resampling for image resizing, on a processor with parallel output units is cast in terms of data access blocks and data coverage charts to increase processor efficiency. Automatic generation of implementations corresponding to input resampling factors by computation cost comparisons.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: February 19, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Ching-Yu Hung
  • Patent number: 7176815
    Abstract: Context-based adapative binary arithmetic coding (CABAC), as used in video standards such as H.264/AVC, with a renormalization of the interval low value plus range that includes partitioning of the bits of the low value to provide output bits plus low value update without bit-level iterations or aggregation of output bits until a full byte can be output.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: February 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-Yu Hung, Shraddha Gondkar, Jagadeesh Sankaran
  • Publication number: 20060007332
    Abstract: A programmable data reformatter reorders output from an image sensor to yield various formats. The reformatting applies to reduced resolution output from large image sensors as in digital cameras operating in video mode, and converts an irregular video mode output to a standard format, such as Bayer pattern, for image processing.
    Type: Application
    Filed: July 9, 2004
    Publication date: January 12, 2006
    Inventors: Deependra Talla, Clay Dunsmore, Ching-Yu Hung
  • Publication number: 20050053131
    Abstract: A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master image processor (30A) captures and encodes a first group of frames, and instructs a slave image processor (30B) to capture and encode a second group of frames presented by the CCD imager (22) before the encoding of the first group of frames is completed by the master image processor. The master image processor (30A) completes its encoding, and is then available to capture and encode another group of frames in the sequence. Video frames that are encoded by the slave image processor (30B) are transferred to the master image processor (30A), which sequences and stores the transferred encoded frames and also those frames that it encodes in a memory (36A; 38).
    Type: Application
    Filed: July 13, 2004
    Publication date: March 10, 2005
    Applicant: Texas Instruments Incorporated
    Inventors: Damon Domke, Youngjun Yoo, Deependra Talla, Ching-Yu Hung
  • Publication number: 20050052463
    Abstract: A method for managing image processing data buffers for processes having overlap input data between iterations includes loading a data buffer with an initial input data array and performing an image data array operation on the input data array. The method repeats the following steps for plural iterations including loading the data buffer with new input data forming a new input data array for a next iteration and performing the input data array operation on the new input data array. The overlap data consists of pixels at an end of each scan line. Loading new input data includes loading pixels following the overlap data for each scan line.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 10, 2005
    Inventor: Ching-Yu Hung
  • Patent number: 6829016
    Abstract: A digital image two-step resizing of filtering an entire image followed by selective row and column deletions. The filtering may use a kernel generated as three samples from a continuous kernel.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: December 7, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Ching-Yu Hung
  • Publication number: 20040145501
    Abstract: Polyphase filtering, such as resampling for image resizing, on a processor with parallel output units is cast in terms of data access blocks and data coverage charts to increase processor efficiency. Automatic generation of implementations corresponding to input resampling factors by computation cost comparisons.
    Type: Application
    Filed: October 22, 2003
    Publication date: July 29, 2004
    Inventor: Ching-Yu Hung
  • Publication number: 20040109185
    Abstract: Tetrahedral interpolation by rewriting the interpolation in terms of ordered differentials and color differences to lower the computational complexity. Additionally, hardward architecture allows efficient implementation.
    Type: Application
    Filed: October 22, 2003
    Publication date: June 10, 2004
    Inventors: Ching-Yu Hung, Deependra Talla
  • Patent number: 6591230
    Abstract: A coprocessor (15) for synthesizing a signal from the sum of sinusoids preferably includes an electronic system (20) having a host processor (12) that forwards frame boundary parameters to the coprocessor (15). Parameter registers (26) in coprocessor (15) store synthesis parameters for iteratively deriving amplitude and phase values for each sample point within a data frame. Adders (28, 30, 32) generate current amplitude from one addition, and current phase value from two additions, with the results stored back into parameter registers (26). A sine function calculator circuit (34), which may use a CORDIC technique, receives the current amplitude and phase values, and generates a digital component signal for the current sample point for one of the sinusoids. Digital component signals are accumulated at the sample point in a data sample buffer (40) and output at an output (44).
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: July 8, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Yinong Ding, Ching-yu Hung
  • Patent number: 6530010
    Abstract: The proposed hardware architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 hardware multiply-accumulate units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: March 4, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-Yu Hung, Leonardo W. Estevez, Wissam A. Rabadi
  • Patent number: 6526430
    Abstract: The proposed architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 multiply-accumulate hardware units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: February 25, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-Yu Hung, Leonardo W. Estevez, Wissam A. Rabadi
  • Publication number: 20020027604
    Abstract: A digital image two-step resizing of filtering an entire image followed by selective row and column deletions. The filtering may use a kernel generated as three samples from a continuous kernel.
    Type: Application
    Filed: December 20, 2000
    Publication date: March 7, 2002
    Inventor: Ching-Yu Hung
  • Patent number: 6327601
    Abstract: A linear transform system (18) for decoding video data is provided. The system (18) includes inputs (50, 52, 54, 56, 58, 60, 62, 64) connected in series to a circuit (40) for implementing a decoding algorithm that includes a multiplication circuit stage (42, 44, 46) having a multiple output scaler structure (82, 84, 86). A bit-serial operator stage (48) is connected in series with the multiplication circuit stage (42, 44, 46). The bit-serial operator stage (48) is coupled to a plurality of outputs (66, 68, 70, 72, 74, 76, 78, 80) that generate decoded video data.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: December 4, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Ching-Yu Hung
  • Patent number: 6298366
    Abstract: A reconfigurable co-processor adapted for multiple multiply-accumulate operations includes plural pairs of multipliers, plural first adders receiving respective product outputs from a pairs of multipliers, and at least one second adder receiving sum outputs from a corresponding pair of first adders. The co-processor includes sign extend circuits at the output of each multiplier. One multiplier of each pair has a fixed left shift circuit that left shifts the product output a predetermined number of bits. The other multiplier in each pair includes a right shift circuit that right shifts the product output the number of bits. Multiplexers at the output of the first multiplier in each pair select the sign extended or the left shifted products. Multiplexers at the output of the second multiplier in each pair select the product, the right shifted product or pass through the inputs. The sign extend circuit for the second multiplier follows the multiplexer.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: October 2, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Alan Gatherer, Carl E. Lemonds, Jr., Dale E. Hocevar, Ching-Yu Hung
  • Patent number: 6263470
    Abstract: A programmable logic device (130) as may be used in a communication system device such as a digital subscriber line modem (408) to perform Reed-Solomon decoding upon a received frame of digital values is disclosed. The programmable logic device (130) may be implemented as a DSP (130) or a general purpose microprocessor, for example. According to one disclosed embodiment of the invention, a group of look-up tables (60) are arranged, each look-up table (60) associated with one of the possible power values of a finite field, number up to twice the number of correctable errors. The contents of each entry (SYN) of the look-up tables (60) correspond to the finite field (e.g., Galois field) multiplication of a primitive element raised to an index power with a character of the finite field alphabet. Galois field multiplications (62) in syndrome accumulation may now be performed with a single table look-up operation.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: July 17, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-Yu Hung, Yaqi Cheng, Tod D. Wolf
  • Patent number: 6256724
    Abstract: A data processing system includes a digital signal processor core and a co-processor. The co-processor has a local memory within the address space of the said digital signal processor core. The co-processor responds commands from the digital signal processor core. A direct memory access circuit autonomously transfers data to and from the local memory of the co-processor. Co-processor commands are stored in a command FIFO memory mapped to a predetermined memory address. Control commands includes a receive data synchronism command stalling the co-processor until completion of a memory transfer into the local memory. A send data synchronism command causes the co-processor to signal the direct memory access circuit to trigger memory transfer out of the local memory. An interrupt command causes the co-processor to interrupt the digital signal processor core.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: July 3, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Dale E. Hocevar, Alan Gatherer, Carl E. Lemonds, Jr., Ching-Yu Hung
  • Patent number: D464656
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: October 22, 2002
    Assignee: Primax Electronics Ltd.
    Inventors: Hui-Yi Lin, Ching-Yu Hung