Patents by Inventor Chittoor Parthasarathy
Chittoor Parthasarathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10634715Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.Type: GrantFiled: May 28, 2019Date of Patent: April 28, 2020Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Vincent Huard, Chittoor Parthasarathy
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Patent number: 10514749Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.Type: GrantFiled: March 23, 2017Date of Patent: December 24, 2019Assignees: STMicroelectonics (Crolles 2) SAS, STMicroelectronics (Alps) SAS, STMicroelectronics SAInventors: Vincent Huard, Silvia Brini, Chittoor Parthasarathy
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Publication number: 20190285694Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.Type: ApplicationFiled: May 28, 2019Publication date: September 19, 2019Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Vincent HUARD, Chittoor PARTHASARATHY
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Patent number: 10302693Abstract: A system-on-a-chip includes an integrated circuit and an estimation circuit. The estimation circuit operates to acquire at least one physical parameter representative of the use of the integrated circuit and determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter. A margin of use of the integrated circuit is then calculated by comparing the instantaneous state of aging with a presumed state of aging.Type: GrantFiled: March 24, 2017Date of Patent: May 28, 2019Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Vincent Huard, Chittoor Parthasarathy
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Publication number: 20180039320Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.Type: ApplicationFiled: March 23, 2017Publication date: February 8, 2018Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Alps) SAS, STMicroelectronics SAInventors: Vincent Huard, Silvia Brini, Chittoor Parthasarathy
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Publication number: 20180038907Abstract: A system-on-a-chip includes an integrated circuit and an estimation circuit. The estimation circuit operates to acquire at least one physical parameter representative of the use of the integrated circuit and determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter. A margin of use of the integrated circuit is then calculated by comparing the instantaneous state of aging with a presumed state of aging.Type: ApplicationFiled: March 24, 2017Publication date: February 8, 2018Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Vincent Huard, Chittoor Parthasarathy
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Patent number: 9798599Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.Type: GrantFiled: February 25, 2015Date of Patent: October 24, 2017Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Chittoor Parthasarathy, Abhishek Jain
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Patent number: 9444440Abstract: An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window. And the second generator is operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window.Type: GrantFiled: June 30, 2011Date of Patent: September 13, 2016Assignee: STMicroelectronics International N.V.Inventors: Abhishek Jain, Kallol Chatterjee, Chittoor Parthasarathy, Saurabhkumar Singh
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Publication number: 20160147545Abstract: An embodiment is a device including a processor having a plurality of cores, each of the plurality of cores including a real-time monitoring circuit, each of the real-time monitoring circuits configured to determine a status of the respective core and generate status signals based on the determined status in the respective core. The device further comprising a controller configured to: receive the status signals from real-time monitoring circuits of the plurality of cores; and configure an operation of each of the plurality of cores based on their respective status signals.Type: ApplicationFiled: November 20, 2014Publication date: May 26, 2016Inventors: Abhishek Jain, Chittoor Parthasarathy
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Patent number: 9160336Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.Type: GrantFiled: December 14, 2012Date of Patent: October 13, 2015Assignee: STMICROELECTRONICS PVT LTDInventors: Abhishek Jain, Chittoor Parthasarathy, Kallol Chatterjee
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Publication number: 20150169394Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.Type: ApplicationFiled: February 25, 2015Publication date: June 18, 2015Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Chittoor Parthasarathy, Abhishek Jain
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Patent number: 9021324Abstract: An arrangement including at least one path, at least one replica path, the at least one replica path corresponding to a respective path, a controller configured to use control information derived from the at least one replica path, at least one of the paths comprising a monitoring unit configured to provide monitor information to the controller, the controller being configured to modify the control information in dependence on the monitor information.Type: GrantFiled: December 21, 2010Date of Patent: April 28, 2015Assignee: STMicroelectronics International N.V.Inventors: Nitin Chawla, Kallol Chatterjee, Chittoor Parthasarathy
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Patent number: 8994416Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.Type: GrantFiled: October 3, 2013Date of Patent: March 31, 2015Assignees: STMicroelectronics International N.V., STMicroelectronics SAInventors: Chittoor Parthasarathy, Nitin Chawla, Kallol Chatterjee, Pascal Urard
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Patent number: 8996937Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.Type: GrantFiled: June 5, 2012Date of Patent: March 31, 2015Assignee: STMicroelectronics International N.V.Inventors: Abhishek Jain, Chittoor Parthasarathy
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Publication number: 20140167812Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: STMicroelectronics International N.V.Inventors: Abhishek Jain, Chittoor Parthasarathy, Kallol Chatterjee
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Publication number: 20140035644Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.Type: ApplicationFiled: October 3, 2013Publication date: February 6, 2014Applicants: STMicroelectronics SA, STMicroelectronics International N.V.Inventors: Chittoor PARTHASARATHY, Nitin CHAWLA, Kallol CHATTERJEE, Pascal URARD
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Patent number: 8552765Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.Type: GrantFiled: June 30, 2011Date of Patent: October 8, 2013Assignees: STMicroelectronics International N.V., STMicroelectronics SAInventors: Chittoor Parthasarathy, Nitin Chawla, Kallol Chatterjee, Pascal Urard
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Publication number: 20130169331Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.Type: ApplicationFiled: June 5, 2012Publication date: July 4, 2013Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Abhishek JAIN, Chittoor PARTHASARATHY
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Publication number: 20130003905Abstract: An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window. And the second generator is operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Abhishek JAIN, Kallol CHATTERJEE, Chittoor PARTHASARATHY, Saurabh Kumar SINGH
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Patent number: RE44922Abstract: An integrated circuit comprising at least one MOS-type transistor, further comprising a system for detecting the variations of the electrical quantities of the at least one transistor, and a biasing device modifying the bias voltage of the bulk of the at least one transistor according to the variations measured by the detection system.Type: GrantFiled: March 3, 2011Date of Patent: June 3, 2014Assignee: STMicroelectronics Crolles 2 SASInventors: Mickael Denais, Vincent Huard, Chittoor Parthasarathy