Patents by Inventor Chiu-Ming Chou
Chiu-Ming Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110049515Abstract: A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.Type: ApplicationFiled: November 7, 2010Publication date: March 3, 2011Applicant: MEGICA CORPORATIONInventors: Nick Kuo, Chiu-Ming Chou, Chien-Kang Chou, Chu-Fu Lin
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Patent number: 7880304Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: GrantFiled: February 13, 2009Date of Patent: February 1, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
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Patent number: 7855461Abstract: A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad.Type: GrantFiled: May 27, 2008Date of Patent: December 21, 2010Assignee: Megica CorporationInventors: Nick Kuo, Chiu-Ming Chou, Chien-Kang Chou, Chu-Fu Lin
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Publication number: 20090291554Abstract: A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.Type: ApplicationFiled: August 4, 2009Publication date: November 26, 2009Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Chiu-Ming Chou
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Patent number: 7592205Abstract: A method for forming a semiconductor chip or wafer includes following steps. A semiconductor substrate is provided, and then a polymer layer is deposited over the semiconductor substrate, wherein the polymer layer comprises polyimide. The polymer layer with a temperature profile having a peak temperature between 200 and 320 degrees Celsius. Alternatively, the temperature profile may comprises a period of time with a temperature higher than 320 degree Celsius, wherein the period of time is shorter than 45 minutes.Type: GrantFiled: July 18, 2005Date of Patent: September 22, 2009Assignee: Megica CorporationInventors: Ying-Chih Chen, Chiu-Ming Chou, Mou-Shiung Lin
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Publication number: 20090218687Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.Type: ApplicationFiled: May 13, 2009Publication date: September 3, 2009Applicant: MEGICA CORPORATIONInventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin
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Patent number: 7582966Abstract: A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.Type: GrantFiled: September 6, 2007Date of Patent: September 1, 2009Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou
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Patent number: 7547969Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.Type: GrantFiled: October 28, 2005Date of Patent: June 16, 2009Assignee: Megica CorporationInventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin
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Publication number: 20090146305Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: ApplicationFiled: February 13, 2009Publication date: June 11, 2009Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
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Publication number: 20090111261Abstract: A method for forming a semiconductor chip or wafer includes following steps. A semiconductor substrate is provided, and then a polymer layer is deposited over the semiconductor substrate, wherein the polymer layer comprises polyimide. The polymer layer with a temperature profile having a peak temperature between 200 and 320 degrees Celsius. Alternatively, the temperature profile may comprises a period of time with a temperature higher than 320 degree Celsius, wherein the period of time is shorter than 45 minutes.Type: ApplicationFiled: November 19, 2008Publication date: April 30, 2009Applicant: MEGICA CORPORATIONInventors: Ying-Chih Chen, Chiu-Ming Chou, Mou-Shiung Lin
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Publication number: 20090108453Abstract: A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.Type: ApplicationFiled: September 1, 2008Publication date: April 30, 2009Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou, Hsin-Jung Lo
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Publication number: 20090104769Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.Type: ApplicationFiled: November 24, 2008Publication date: April 23, 2009Applicant: MEGICA CORPORATIONInventors: Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee
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Patent number: 7521805Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: GrantFiled: October 23, 2007Date of Patent: April 21, 2009Assignee: Megica Corp.Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
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Patent number: 7508059Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.Type: GrantFiled: May 3, 2006Date of Patent: March 24, 2009Assignee: Megica CorporationInventors: Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen, Chiu-Ming Chou
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Publication number: 20090057894Abstract: A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first metal layer exposed by an opening in said first mask layer. Said first mask layer is removed. A second mask layer is deposited over said second metal layer. A third metal layer is deposited over said second metal layer exposed by an opening in said second mask layer. Said second mask layer is removed. Said first metal layer not covered by said second metal layer is removed.Type: ApplicationFiled: October 31, 2008Publication date: March 5, 2009Applicant: MEGICA CORPORATIONInventors: Chiu-Ming Chou, Mou-Shiung Lin
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Publication number: 20090057900Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.Type: ApplicationFiled: November 12, 2008Publication date: March 5, 2009Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen, Chiu-Ming Chou
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Patent number: 7482268Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.Type: GrantFiled: October 23, 2007Date of Patent: January 27, 2009Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
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Patent number: 7470927Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.Type: GrantFiled: May 17, 2006Date of Patent: December 30, 2008Assignee: Megica CorporationInventors: Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee
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Patent number: 7465654Abstract: A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first metal layer exposed by an opening in said first mask layer. Said first mask layer is removed. A second mask layer is deposited over said second metal layer. A third metal layer is deposited over said second metal layer exposed by an opening in said second mask layer. Said second mask layer is removed. Said first metal layer not covered by said second metal layer is removed.Type: GrantFiled: July 11, 2005Date of Patent: December 16, 2008Assignee: Megica CorporationInventors: Chiu-Ming Chou, Mou-Shiung Lin
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Patent number: 7462558Abstract: A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.Type: GrantFiled: February 2, 2008Date of Patent: December 9, 2008Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou, Hsin-Jung Lo