Patents by Inventor Chok J. Chia

Chok J. Chia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190148324
    Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier. The conductive structure can include a base and a plurality of interconnections extending continuously away from the base toward the carrier. The microelectronic element can be positioned between at least two adjacent interconnections of the plurality of interconnections. The conductive structure may be bonded to the carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The plurality of interconnections and the microelectronic element may be encapsulated. The carrier may be removed to expose free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and bond pads of the microelectronic element may be conductively connected with terminals of the microelectronic package. The conductive structure may be patterned to form external contacts.
    Type: Application
    Filed: January 11, 2019
    Publication date: May 16, 2019
    Applicant: Invensas Corporation
    Inventors: Chok J. Chia, Qwai H. Low, Patrick Variot
  • Patent number: 10181447
    Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 15, 2019
    Assignee: Invensas Corporation
    Inventors: Chok J. Chia, Qwai H. Low, Patrick Variot
  • Publication number: 20180308813
    Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Inventors: Chok J. Chia, Qwai H. Low, Patrick Variot
  • Patent number: 9875955
    Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: January 23, 2018
    Assignee: Tessera, Inc.
    Inventors: Kishor Desai, Qwai H. Low, Chok J. Chia, Charles G. Woychik, Huailiang Wei
  • Publication number: 20170077018
    Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.
    Type: Application
    Filed: November 28, 2016
    Publication date: March 16, 2017
    Inventors: Kishor DESAI, Qwai H. LOW, Chok J. CHIA, Charles G. WOYCHIK, Huailiang WEI
  • Patent number: 9508687
    Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: November 29, 2016
    Assignee: Tessera, Inc.
    Inventors: Kishor Desai, Qwai H. Low, Chok J. Chia, Charles G. Woychik, Huailiang Wei
  • Publication number: 20150171058
    Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.
    Type: Application
    Filed: February 23, 2015
    Publication date: June 18, 2015
    Inventors: Kishor Desai, Qwai H. Low, Chok J. Chia, Charles G. Woychik, Huailiang Wei
  • Patent number: 8963310
    Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: February 24, 2015
    Assignee: Tessera, Inc.
    Inventors: Kishor Desai, Qwai H. Low, Chok J. Chia, Charles G. Woychik, Huailiang Wei
  • Patent number: 8525312
    Abstract: A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: September 3, 2013
    Assignee: Tessera, Inc.
    Inventors: Qwai H. Low, Chok J. Chia, Kishor Desai, Charles G. Woychik, Huailiang Wei
  • Publication number: 20130049179
    Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: TESSERA, INC.
    Inventors: Kishor Desai, Qwai H. Low, Chok J. Chia, Charles G. Woychik, Huailiang Wei
  • Publication number: 20130037925
    Abstract: A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.
    Type: Application
    Filed: August 12, 2011
    Publication date: February 14, 2013
    Applicant: TESSERA, INC.
    Inventors: Qwai H. Low, Chok J. Chia, Kishor Desai, Charles G. Woychik, Huailiang Wei
  • Patent number: 8129759
    Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: March 6, 2012
    Assignee: LSI Logic Corporation
    Inventors: Maurice O. Othieno, Chok J. Chia, Amar J. Amin
  • Patent number: 7804167
    Abstract: An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: September 28, 2010
    Assignee: LSI Logic Corporation
    Inventors: Clifford Fishley, Abiola Awujoola, Leonard Mora, Amar Amin, Maurice Othieno, Chok J. Chia
  • Publication number: 20100067207
    Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
    Type: Application
    Filed: November 24, 2009
    Publication date: March 18, 2010
    Applicant: LSI CORPORATION
    Inventors: Maurice O. Othieno, Chok J. Chia, Amar J. Amin
  • Patent number: 7646091
    Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: January 12, 2010
    Assignee: LSI Corporation
    Inventors: Maurice O. Othieno, Chok J. Chia, Amar J. Amin
  • Publication number: 20080128919
    Abstract: An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 5, 2008
    Inventors: Clifford Fishley, Abiola Awujoola, Leonard Mora, Amar Amin, Maurice Othieno, Chok J. Chia
  • Patent number: 7327043
    Abstract: A routing pattern for high speed signals for a package substrate. Electrically conductive bond fingers are disposed on a first surface of the package substrate. The first surface is adapted to receive an integrated circuit in an attachment zone, and the bond fingers are disposed in at least two substantially concentric rings around the attachment zone. The bond fingers of the innermost ring of bond fingers are all routed to electrically conductive first traces disposed on a first layer of the package substrate. The bond fingers other that those on the innermost ring of bond fingers are all routed to electrically conductive second traces disposed on a separate second layer of the package substrate. The package substrate has electrically conductive traces on only the first layer and the second layer. Electrically conductive contacts are disposed on a substantially opposing second surface.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: February 5, 2008
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Allen Seng Sooi Lim, Maurice O. Othieno
  • Patent number: 6991147
    Abstract: A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: January 31, 2006
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Owai H. Low, Ramaswamy Ranganathan
  • Patent number: 6963138
    Abstract: An integrated circuit with a pressure resistant current carrying structure having electrically conductive layers for carrying current. A first electrically nonconductive material at least partially surrounds the electrically conductive layers, and provides electrical insulation between the electrically conductive layers. The first electrically nonconductive material has a first degree of fragility and a first dielectric constant. A second electrically nonconductive material is disposed in a pattern within the first electrically nonconductive material and between the electrically conductive layers, and provides structural support for the first electrically nonconductive material between the electrically conductive layers. The second electrically nonconductive material has a second degree of fragility that is less than the first degree of fragility and a second dielectric constant that is greater than the first dielectric constant.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: November 8, 2005
    Assignee: LSI Logic Corporation
    Inventors: Qwai H. Low, Chok J. Chia, Ramaswamy Ranganathan, Tauman T. Lau
  • Patent number: 6861343
    Abstract: An integrated circuit having a top passivation layer and bonding pads, where the improvement is a metal layer overlying all of the integrated circuit. The metal layer overlies the top passivation layer and is not in electrical contact with any of the bonding pads. In this manner, there is a structure that is added to the integrated circuit which has a relatively high thermal conductivity, and which also has a relatively high structural strength. With these two added properties, the occurrence of stress cracks, such as those induced by plastic molded packages, is reduced, and hot spots tend to be dissipated. Thus, the overlying metal layer tends to improve the reliability of the integrated circuit.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: March 1, 2005
    Inventors: Chok J. Chia, Qwai H. Low, Ramaswamy Ranganathan