Patents by Inventor Chok J. Chia

Chok J. Chia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6114749
    Abstract: An integrated circuit includes a semiconductor integrated circuit chip housed in a package providing external electrical connections for the circuit chip. The package has only a limited number of external connections available for such use. The package includes an internal buss, or plurality of busses, which are electrically connected to the circuit chip and to selected external connections of the package to improve the efficiency of utilization of external connections on the package, as well as improving operating characteristics of the integrated circuit chip by improvements to voltage and current distributions to the chip, and also eliminating in some cases the consequences of a poor quality of external electrical connection to the package itself.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: September 5, 2000
    Assignee: LSI Loigc Corporation
    Inventor: Chok J. Chia
  • Patent number: 6110815
    Abstract: A method of electroplating a high density integrated circuit (IC) substrate using a conductive elastomer including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces with conductive trace lands formed on its surface. Covering only the traces (not the trace lands) with a plating resist and exposing portions of the conductive traces. Inserting the IC substrate into a electroplating fixture. Engaging a conductive elastomer to the IC substrate, covering the plurality of conductive traces and electrically connecting all of the traces together. Electroplating the trace lands on the IC substrate with conductive material (such as gold or nickel) by using the conductive elastomer as the electrical connection to the trace lands (via the exposed metal traces). Disengaging the conductive elastomer after electroplating is finished and removing the IC substrate from the electroplating fixture.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: August 29, 2000
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Patrick Variot, Maniam Alagaratnam
  • Patent number: 6088914
    Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: July 18, 2000
    Assignee: LSI Logic Corporation
    Inventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
  • Patent number: 6081997
    Abstract: A system and method are presented for forming a grid array device package around an integrated circuit. The integrated circuit includes multiple I/O pads on an underside surface, and an upper surface of a substrate includes a corresponding set of bonding pads. The substrate also has an opening (i.e., a hole) extending therethrough and preferably substantially in the center of the set of bonding pads. Solder bumps formed upon the I/O pads of the integrated circuit are placed in direct contact with corresponding members of the set of bonding pads, then heated until they flow in a C4 connection method. Following C4 connection of the I/O and bonding pads, the substrate and the attached integrated circuit are positioned within a mold cavity formed between two mold sections, and a liquid encapsulant material is injected through the opening of the substrate such that the encapsulant fills the mold cavity. The coupled I/O and bonding pads are enveloped by the liquid encapsulant.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: July 4, 2000
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng Sooi Lim, Maniam Alagaratnam
  • Patent number: 6057594
    Abstract: A molded tape ball grid array package has a base structure including a heat conductive substrate and flex tape extending from opposing regions on a surface of the substrate with molded plastic material between the flex tape and the substrate. The flex tape has at least one conductive metal lead pattern which can be positioned on a side of the tape facing the substrate with a plurality of apertures exposing the conductive lead pattern from an opposing side of the tape for solder ball bonding. A semiconductor integrated circuit chip is mounted to a central portion of the substrate between the opposing regions of the flex tape with wire bonding interconnecting bond pads on the chip to the metal lead pattern. The chip and wire bonding are then encapsulated on the substrate. The structure is economical and permits high power dissipation from an integrated circuit. The molding process in fabricating the integrated circuit package is economical and readily implemented using injection molding.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: May 2, 2000
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Qwai H. Low, Maniam Alagaratnam
  • Patent number: 6054767
    Abstract: A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g.
    Type: Grant
    Filed: January 13, 1998
    Date of Patent: April 25, 2000
    Assignee: LSI Logic Corp.
    Inventors: Chok J. Chia, Seng-Sooi Lim, Patrick Variot
  • Patent number: 6040632
    Abstract: A multiple-sized integrated circuit (IC) die and a method of making a multiple-sized IC die includes forming a plurality of IC dies on a semiconductor wafer. Each IC die has multiple rows of bonding pads around its periphery. Adjacent bonding pads on separate rows of each IC die are electrically connected together so that attachment to any one of the connected bond pads yields the same result. A plurality of scribe streets separate each IC die on the wafer, with the scribe street defining the width between each IC die. Rows of bonding pads reside in the scribe street area. Different rows of bonding pads may be selectively removed from the IC die by scribing the wafer so as to include one or more of the rows of bonding pads, thereby allowing one IC die design to have multiple sizes. An IC die separated from the wafer may still be sized smaller as long as there remain at least two rows of bonding pads around the periphery.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: March 21, 2000
    Assignee: LSI Logic Corporation
    Inventors: Qwai H. Low, Chok J. Chia, Seng-Sooi Lim
  • Patent number: 6002169
    Abstract: A semiconductor package (110) includes a tape substrate (135) having a top surface, a bottom surface, a plurality of conductive metal traces (115) formed on the top surface and a plurality of holes (130) arraigned in an array pattern formed through the tape substrate (135) exposing the conductive traces (115) from the bottom surface. A nonconductive metal plate or stiffener frame (155) attached to the bottom surface of the tape substrate (135) to support the tape substrate (135) during assembly. The stiffener frame (155) having through holes (160) corresponding to the holes (130) in the tape substrate (135) and being made from anodized aluminum, thus making it electrically nonconductive. An integrated circuit (IC) chip (120) is mounted on the top surface, opposite the stiffener frame (155).
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: December 14, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim, Owai H. Low
  • Patent number: 5989937
    Abstract: An integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: November 23, 1999
    Assignee: LSI Logic Corporation
    Inventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
  • Patent number: 5981311
    Abstract: A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: November 9, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng Sooi Lim, Patrick Variot
  • Patent number: 5973397
    Abstract: A semiconductor device and fabrication method are presented which advantageously combine TAB and wire bonding techniques to increase integrated circuit I/O pad density. The semiconductor device includes an integrated circuit, a substrate, and a carrier film (i.e., a TAB tape). The integrated circuit has a set of input/output (I/O) pads arranged upon an upper surface. The substrate has a die cavity within an upper surface and a set of bond traces arranged about the die cavity. An underside surface of the integrated circuit is attached to the substrate within the die cavity. The carrier film is positioned over the upper surface of the substrate such that the upper surface of the integrated circuit is exposed through a die aperture and portions of the members of the set of bond traces are exposed through corresponding members of a set of bond trace apertures.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: October 26, 1999
    Assignee: LSI Logic Corporation
    Inventors: Qwai H. Low, Chok J. Chia, Seng-Sooi Lim
  • Patent number: 5973393
    Abstract: An apparatus and method for packaging an integrated circuit having a semiconductor die with electronic circuitry disposed thereon includes lead frames for mounting thereon solder balls of a ball grid array packaging structure. In one embodiment, the semiconductor die is coupled to conductors of the lead frame via gold wires attached to both the semiconductor die and the lead frame. The lead frame is encapsulated in plastic with apertures disposed therein for exposing upper and lower portions of conductors of the lead frame. The apertures are filled with solder balls to contact both the upper and lower portions of the lead frame conductors. Solder balls on the top of one integrated circuit package may be connected to mating solder balls on the bottom of another integrated circuit package, and so on, thereby achieving multiple stacking of integrated circuit packages.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: October 26, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim, Qwai H. Low
  • Patent number: 5933710
    Abstract: A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: August 3, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Patrick Variot
  • Patent number: 5927505
    Abstract: Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: July 27, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim, Maniam Alagaratnam
  • Patent number: 5923047
    Abstract: The testing of integrated circuits in a plurality of dice arranged in rows and columns in a semiconductor wafer is facilitated by effectively increasing the pitch between adjacent input/output bonding pads on each die by providing a plurality of test pads in scribing space between adjacent die. Alternate test pads are connected with alternate bonding pads on adjacent die, thereby effectively increasing the pitch of adjacent die for testing. After the integrated circuits are tested and defective circuits are marked, the wafer is scribed in the scribe space and broken to recover the individual die or integrated circuit chips.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: July 13, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Qwai H. Low, Maniam Alagaratnam
  • Patent number: 5901437
    Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: May 11, 1999
    Assignee: LSI Logic Corporation
    Inventors: Patrick Variot, Chok J. Chia, Robert T. Trabucco
  • Patent number: 5886398
    Abstract: According to the present invention, a semiconductor package is provided. In one version of the invention, the semiconductor package includes a laminated substrate having a semiconductor die mounted on its upper surface, electrical connections between bond pads on the semiconductor die and conductive traces on the substrate, as well as electrical connections between the conductive traces and electrical contacts on the lower surface of the substrate. The semiconductor package also includes a molded covering on the upper surface of the substrate which covers the semiconductor die and the electrical connections. The molded covering has a mold body portion and a mold gate runner which extends from the mold body portion to an edge of the substrate. The mold gate runner is provided with a surface that is substantially even with the edge of the substrate and rises perpendicularly from the upper surface of the substrate.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: March 23, 1999
    Assignee: LSI Logic Corporation
    Inventors: Qwai H. Low, Manickam Thavarajah, Chok J. Chia, Maniam Alagaratnam
  • Patent number: 5869889
    Abstract: An integrated circuit package includes a heatspreader which is formed to have a centrally disposed recessed portion between planar surfaces, and flex tape extending from the planar surfaces into the centrally disposed surface. A semiconductor chip is mounted on the centrally disposed surface between the flex tape, and wire bonds interconnect bonding pads on the chip to the metal interconnect patterns on the flex tape. Plastic molding or epoxy is then applied to encapsulate the chip and wire bonding in the centrally disposed planar surface of the heat spreader. The package is then readily mounted on a motherboard using solder balls.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: February 9, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Patrick Variot, Maniam Alagaratnam
  • Patent number: 5841198
    Abstract: A ball grid array package utilizes solder balls having central cores of a material with a higher melting point than solder material surrounding the core. When the ball grid package and motherboard assembly are heated to the melting point of the solder material, the cores remain solid and function as spacers in preventing direct contact of the package surface and the motherboard surface, thus preventing molten solder from being squashed and flowing to adjacent ball contacts.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: November 24, 1998
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Patrick Variot, Maniam Alagaratnam
  • Patent number: 5841191
    Abstract: A ball grid array package in which one or more conductive rings are positioned on a surface of the package substrate along with solder bond contacts on the surface of the substrate to facilitate the interconnection of wire bonds to an integrated circuit chip on the surface of the substrate. The use of rings allows for better distribution of power to the chip since a plurality of wires can be connected between the chip and the conductive rings for power distribution. The rings create a different shelf for the power and ground bonds on the substrate, and by providing a vertical separation between the surfaces of the rings and bonding pads on the surface of the substrate more bonds in the package can be accommodated.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: November 24, 1998
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Qwai H. Low, Maniam Alagaratnam