Patents by Inventor Chok J. Chia

Chok J. Chia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4778641
    Abstract: A pin-grid package is created by starting with printed wiring boards that have plated through holes that can accommodate wire pins. Pins are secured in position to extend outward from one face of the PW board in the form of a pin grid array of the desired configuration which is typically a plurality of concentric rings thereby creating a square grid pattern of predetermined spacing. The opposing PW board face includes a central pin-free area to which is secured a semiconductor die. This face of the PW board includes a plurality of wiring traces that connect each pin to an array that surrounds the semiconductor die. The traces are connected to the bonding pads of the semiconductor die by either wire bonds or a spider assembly using tape assembly bonding. The PW board is located in a mold that has a flat faced first platen that contains cut-out regions that will accommodate the package pins.
    Type: Grant
    Filed: June 18, 1987
    Date of Patent: October 18, 1988
    Assignee: National Semiconductor Corporation
    Inventor: Chok J. Chia
  • Patent number: 4688152
    Abstract: A pin-grid package is created by starting with printed wiring boards that have plated through holes that can accommodate wire pins. Pins are secured in position to extend outward from one face of the PW board in the form of a pin grid array of the desired configuration which is typically a plurality of concentric rings thereby creating a square grid pattern of predetermined spacing. The opposing PW board face includes a central pin-free area to which is secured a semiconductor die. This face of the PW board includes a plurality of wiring traces that connect each pin to an array that surrounds the semiconductor die. The traces are connected to the bonding pads of the semiconductor die by either wire bonds or a spider assembly using tape assembly bonding. The PW board is located in a mold that has a flat faced first platen that contains cut-out regions that will accommodate the package pins.
    Type: Grant
    Filed: August 11, 1986
    Date of Patent: August 18, 1987
    Assignee: National Semiconductor Corporation
    Inventor: Chok J. Chia