Abstract: An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.

Abstract: An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller. The apparatus has a configurable information memory and comprises: an access control input port via which the apparatus receives a data access command from the host controller; a control unit to identify a data access command including an access address directed to a predetermined storage region of the memory module, and generate an information processing command based at least on the access address directed to the predetermined storage region, such that the control unit can configure the information memory based on the information processing command or provide the information processing command to the memory module; and an access control output port via which the apparatus provides the information processing command to the memory module, such that the memory module outputs corresponding data information to the host controller based on the information processing command.

Abstract: An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.

Abstract: A memory controller and a method for accessing a memory module are provided. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving a data access command from the host controller, and coupled to the memory module for providing a modified data access command to the memory module; wherein the central buffer comprises an access command processing module, for processing the data access command to generate the modified data access command; and a data buffer coupled to the central buffer for receiving the modified data access command from the central buffer, and coupled between the host controller and the memory module for exchanging data between the host controller and the memory module under the control of the modified data access command.

Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module. The memory controller comprises: a registering clock driver coupled to the memory module for providing a data access command to the memory module so as to control access to the memory module; and a data buffer coupled between the registering clock driver and the memory module for exchanging data between the memory module and the registering clock driver under the control of the registering clock driver; wherein the registering clock driver comprises a computing unit for computing the data received via the data buffer from the memory module and providing a computing result to the memory module via the data buffer.

Abstract: A data conversion control apparatus, comprising: at least one first interface each for coupling a first external interface, both of the first interface and the first external interface being in accordance with a predetermined physical interface standard, wherein data transmitted between the first interface and the first external interface is in accordance with a configurable application layer protocol; at least one second interface each for coupling a second external interface, wherein the second external interface is a memory interface in accordance with a predetermined memory interface standard, and the second interface is configurable to match the predetermined memory interface standard; and a data rebuild unit coupled between the at least one first interface and the at least one second interface, wherein the data rebuild unit is configured to rebuild data such that data can be transmitted in respective formats between the at least one first interface and the at least one second interface.

Abstract: The application discloses a memory controller and a method for controlling an access to a memory module. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving data access command from the host controller and coupled to the memory module for providing an encrypted data access command to the memory module; wherein the central buffer comprises a command processing module, for performing encryption operation to a data access command with a predefined command encryption algorithm to generate an encrypted data access command; wherein a data channel is coupled between the memory module and the host controller, and wherein under the control of the encrypted data access command, the memory module exchanges data with the host controller via the data channel.

Abstract: The application discloses a memory controller and a method for controlling an access to a memory module. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving data access command from the host controller and coupled to the memory module for providing an encrypted data access command to the memory module; wherein the central buffer comprises a command processing module, for performing encryption operation to a data access command with a predefined command encryption algorithm to generate an encrypted data access command; wherein a data channel is coupled between the memory module and the host controller, and wherein under the control of the encrypted data access command, the memory module exchanges data with the host controller via the data channel.

Abstract: A memory controller and a method for accessing a memory module are provided. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving a data access command from the host controller, and coupled to the memory module for providing a modified data access command to the memory module; wherein the central buffer comprises an access command processing module, for processing the data access command to generate the modified data access command; and a data buffer coupled to the central buffer for receiving the modified data access command from the central buffer, and coupled between the host controller and the memory module for exchanging data between the host controller and the memory module under the control of the modified data access command.

Abstract: A data conversion control apparatus, comprising: at least one first interface each for coupling a first external interface, both of the first interface and the first external interface being in accordance with a predetermined physical interface standard, wherein data transmitted between the first interface and the first external interface is in accordance with a configurable application layer protocol; at least one second interface each for coupling a second external interface, wherein the second external interface is a memory interface in accordance with a predetermined memory interface standard, and the second interface is configurable to match the predetermined memory interface standard; and a data rebuild unit coupled between the at least one first interface and the at least one second interface, wherein the data rebuild unit is configured to rebuild data such that data can be transmitted in respective formats between the at least one first interface and the at least one second interface.

Abstract: An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller. The apparatus has a configurable information memory and comprises: an access control input port via which the apparatus receives a data access command from the host controller; a control unit to identify a data access command including an access address directed to a predetermined storage region of the memory module, and generate an information processing command based at least on the access address directed to the predetermined storage region, such that the control unit can configure the information memory based on the information processing command or provide the information processing command to the memory module; and an access control output port via which the apparatus provides the information processing command to the memory module, such that the memory module outputs corresponding data information to the host controller based on the information processing command.

Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module. The memory controller comprises: a registering clock driver coupled to the memory module for providing a data access command to the memory module so as to control access to the memory module; and a data buffer coupled between the registering clock driver and the memory module for exchanging data between the memory module and the registering clock driver under the control of the registering clock driver; wherein the registering clock driver comprises a computing unit for computing the data received via the data buffer from the memory module and providing a computing result to the memory module via the data buffer.

Abstract: A memory controller and a method for accessing a memory module are provided. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving a data access command from the host controller, and coupled to the memory module for providing a modified data access command to the memory module; wherein the central buffer comprises an access command processing module, for processing the data access command to generate the modified data access command; and a data buffer coupled to the central buffer for receiving the modified data access command from the central buffer, and coupled between the host controller and the memory module for exchanging data between the host controller and the memory module under the control of the modified data access command.

Abstract: A memory controller and a method for accessing a memory module are provided. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving a data access command from the host controller, and coupled to the memory module for providing a modified data access command to the memory module; wherein the central buffer comprises an access command processing module, for processing the data access command to generate the modified data access command; and a data buffer coupled to the central buffer for receiving the modified data access command from the central buffer, and coupled between the host controller and the memory module for exchanging data between the host controller and the memory module under the control of the modified data access command.

Abstract: The application discloses a memory controller and a method for controlling an access to a memory module. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving data access command from the host controller and coupled to the memory module for providing an encrypted data access command to the memory module; wherein the central buffer comprises a command processing module, for performing encryption operation to a data access command with a predefined command encryption algorithm to generate an encrypted data access command; wherein a data channel is coupled between the memory module and the host controller, and wherein under the control of the encrypted data access command, the memory module exchanges data with the host controller via the data channel.

Abstract: The application discloses a memory controller and a method for controlling an access to a memory module. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving data access command from the host controller and coupled to the memory module for providing an encrypted data access command to the memory module; wherein the central buffer comprises a command processing module, for performing encryption operation to a data access command with a predefined command encryption algorithm to generate an encrypted data access command; wherein a data channel is coupled between the memory module and the host controller, and wherein under the control of the encrypted data access command, the memory module exchanges data with the host controller via the data channel.

Abstract: The application discloses a buffer device and a method for controlling data access to an internal memory. The buffer device has a central buffer module coupled to a memory interface to receive a command/address signal via a command/address channel. The central buffer module is configured to detect whether a destination address of the received command/address signal is within a predefined address space, and generate a security read/write signal when the command/address signal is within the predefined address space. The buffer device further has a data buffer module coupled between the memory interface and a memory module to buffer data therebetween. The data buffer module is configured to store reference data, compare the buffered data with the reference data in response to the security read/write signal, and determine whether or not to restrict exchange of the buffered data between the memory module and the memory interface.

Abstract: The application discloses a buffer device and a method for controlling data access to an internal memory. The buffer device has a central buffer module coupled to a memory interface to receive a command/address signal via a command/address channel. The central buffer module is configured to detect whether a destination address of the received command/address signal is within a predefined address space, and generate a security read/write signal when the command/address signal is within the predefined address space. The buffer device further has a data buffer module coupled between the memory interface and a memory module to buffer data therebetween. The data buffer module is configured to store reference data, compare the buffered data with the reference data in response to the security read/write signal, and determine whether or not to restrict exchange of the buffered data between the memory module and the memory interface.

Abstract: An information insertion method and system are provided. The method includes: determining whether an insertion interval starts when a presentation module presents information from a first information source apparatus; when the interval starts, transmitting information from a second information source apparatus, preferably a local apparatus, into the presentation module for presentation; and when the interval ends, stopping transmission of information from the second apparatus into the presentation module, so that the module stops presenting information from the second apparatus and presents information from the first apparatus, thereby preventing the problem caused by channel switching or network congestion resulting in no image on the screen or temporary appearance of a screensaver image.