Abstract: A method of forming fine patterns according to an aspect of the present disclosure comprises stacking a hard mask layer and a first auxiliary layer over an underlying layer, removing regions of the first auxiliary layer, thereby forming first auxiliary patterns to expose regions of the hard mask layer, filling between the first auxiliary patterns with a second auxiliary layer, wherein a material of the second auxiliary layer is different from that of the first auxiliary layer, lowering a height of the second auxiliary layer by removing the second auxiliary layer to expose sidewalls of the first auxiliary patterns, forming spacers on the exposed sidewalls of the first auxiliary patterns to expose regions of the second auxiliary layer, wherein a material of the spacers is different from that of the second auxiliary layer, removing the exposed regions of the second auxiliary layer, removing the spacers and the first auxiliary patterns to expose regions of the hard mask layer and removing the exposed regions of t

Abstract: In a method of fabricating a flash memory device, trenches are formed in an isolation area of a semiconductor substrate. A first insulating layer is formed on sidewalls and bottoms of the trenches. Conductive layer patterns are formed on the first insulating layers at the bottoms of the trenches. A second insulating layer is formed on the conductive layer patterns. Gate lines are formed over a semiconductor substrate including the second insulating layer. The gate lines intersect the conductive layer patterns. Junctions are formed on the semiconductor substrate between the gate lines. An interlayer insulating layer is formed over the semiconductor substrate including the gate lines. Contact holes are formed through which the conductive layer patterns and the junctions located on one side of the conductive layer patterns are exposed. The contact holes are gap-filled with a conductive material, thereby forming contact plugs.

Abstract: In a method of fabricating a semiconductor device, an additive gas is mixed with an etching gas to reduce a fluorine ratio of the etching gas. The etching gas having a reduced fluorine rate is utilized in the process for etching a nitride layer formed on an oxide layer to prevent the oxide layer formed below the nitride layer from being etched along with the nitride layer. The method comprises primarily etching an exposed charge storage layer using an etching gas; and secondarily etching the charge storage layer using the etching gas under a condition that a ratio of fluorine contained in the etching gas utilized in the secondary etching step is less than a ratio of fluorine contained in the etching gas utilized in the primary etching step. Thus, the tunnel insulating layer formed below the charge storage layer is not damaged when the charge storage layer is patterned.

Abstract: In a method of fabricating a semiconductor device, an additive gas is mixed with an etching gas to reduce a fluorine ratio of the etching gas. The etching gas having a reduced fluorine rate is utilized in the process for etching a nitride layer formed on an oxide layer to prevent the oxide layer formed below the nitride layer from being etched along with the nitride layer. The method comprises primarily etching an exposed charge storage layer using an etching gas; and secondarily etching the charge storage layer using the etching gas under a condition that a ratio of fluorine contained in the etching gas utilized in the secondary etching step is less than a ratio of fluorine contained in the etching gas utilized in the primary etching step. Thus, the tunnel insulating layer formed below the charge storage layer is not damaged when the charge storage layer is patterned.

Abstract: A method of manufacturing a semiconductor device comprises providing a semiconductor substrate, forming trenches in predetermined regions of the semiconductor substrate, forming isolation structures within the trenches that separate active regions and field regions of the device, and etching exposed regions of the semiconductor substrate so that the exposed regions of possess a curved surface. In a specific embodiment of the invention, an oxidization process is performed to compensate for damage on the exposed regions of the semiconductor substrate after etching the semiconductor substrate, and a wet etch process is performed to remove an oxide layer grown by the oxidization process. In a specific embodiment of the invention, the etch process may comprise a wet or dry etch process.

Abstract: In a method of fabricating a semiconductor device, a charge storage layer is etched using an etching gas by which a tunnel insulating layer is less etched than the charge storage layer. Thus, it is possible to prevent the tunnel insulating layer formed below the charge storage layer from being damaged when the charge storage layer is patterned. The method of fabricating a semiconductor device includes providing a semiconductor substrate on which a tunnel insulating layer and a charge storage layer formed of an insulating material are formed; forming a stack layer on the charge storage; patterning the stack layer to expose a portion of the charge storage layer; and etching the exposed charge storage layer using as etching gas hydrogen bromide (HBr) gas, chloride (Cl2) gas, hydrogen chloride (HCl) gas or a mixture gas thereof.

Abstract: The present invention relates to a method of forming trenches of a semiconductor device. According to the method, a hard mask pattern is formed on a semiconductor substrate so that an isolation region of the semiconductor substrate is opened. First trenches are formed in the isolation region by performing a first etch process employing the hard mask pattern. A spacer is formed on sidewalls of the first trenches. Second trenches, having a depth deeper than that of the first trenches, are formed in the isolation region by performing a second etch process employing the hard mask pattern.

Abstract: In a method of fabricating a flash memory device, trenches are formed in an isolation area of a semiconductor substrate. A first insulating layer is formed on sidewalls and bottoms of the trenches. Conductive layer patterns are formed on the first insulating layers at the bottoms of the trenches. A second insulating layer is formed on the conductive layer patterns. Gate lines are formed over a semiconductor substrate including the second insulating layer. The gate lines intersect the conductive layer patterns. Junctions are formed on the semiconductor substrate between the gate lines. An interlayer insulating layer is formed over the semiconductor substrate including the gate lines. Contact holes are formed through which the conductive layer patterns and the junctions located on one side of the conductive layer patterns are exposed. The contact holes are gap-filled with a conductive material, thereby forming contact plugs.

Abstract: A method of manufacturing semiconductor devices, including the steps of forming an interlayer insulating layer over a semiconductor substrate in which a predetermined structure including a drain is formed, etching a part of the interlayer insulating layer to form a contact hole, and then forming a first conductive film on the entire structure including the contact hole, blanket-etching the first conductive film so that the first conductive film remains on a surface of the contact hole, forming a second conductive film on the entire structure, burying a contact hole, and then performing a blanket-etch or CMP process using the interlayer insulating layer as a stopper, and forming a metal line layer on the entire structure.