Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract: Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area.

Abstract: A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.

Abstract: A display apparatus having an improved function for encapsulating a display unit, and comprising a substrate, wherein the display unit is disposed on the substrate; an encapsulation unit facing the display unit, the encapsulation unit comprising: a metal layer; and a composite member; and a sealing unit disposed between the substrate and the encapsulation unit and separated from the display unit so as to adhere the substrate to the encapsulation unit, wherein the composite member comprises a resin matrix and carbon fibers, and wherein the metal layer is disposed between the substrate and the composite member.

Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.

Abstract: A mask frame assembly for thin film deposition, the mask frame assembly including a frame having an opening; a plurality of masks having deposition patterns, the masks being fixed to the frame such that the deposition patterns extend over the opening; and a balance stick being fixed to the frame such that the balance stick is between two of the plurality of masks, the balance stick made from an elastically tensile material.

Abstract: Provided are a selection transistor and a method of fabricating the same. A selection transistor can be formed on an active region in a semiconductor substrate to include a gate electrode that includes recessed portions of a sidewall of the gate electrode which are recessed inward adjacent lower portions of the gate electrode to define a T-shaped cross section of the gate electrode. A tunnel insulating layer can be located between the gate electrode and the active region.

Abstract: A mask frame assembly for thin film deposition includes a frame having an opening and at least two unit masks having end parts in a longitudinal direction fixed to the frame, each of the unit masks comprising first regions and second regions, the first regions having unit masking patterns, each of the unit masking patterns having a plurality of openings for thin film deposition, the unit masking pattern being spaced apart from each other, each of the second regions being interposed between a pair of adjacent ones of the first regions, the first regions having a first thickness from a first surface of the unit masks, and at least a portion of the second regions having a second thickness from a second surface of the unit masks opposite to the first surface of the unit masks, such that the first regions and the at least the portion of the second regions are offset from each other in a direction normal to the first and second surfaces.

Abstract: Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate.

Abstract: A non-volatile memory device includes a selection transistor coupled to a bit line. The device also includes a plurality of memory cells serially coupled to the selection transistor and at least one dummy cell located between the plurality of memory cells. The dummy cell is turned off during a programming operation of a memory cell located between the dummy cell and the selection transistor.

Abstract: A frit sealing system and a method of manufacturing an organic light-emitting display (OLED) using the frit sealing system are disclosed. In one embodiment, the frit sealing system includes: a thermal expansion film formed on the second substrate to pressurize the second substrate when heat is applied to the frit and thermal expansion film, wherein the frit is interposed between the first and second substrates and a mask formed on the thermal expansion film.

Abstract: A method of efficiently manufacturing a large-sized mask is disclosed. In one embodiment, the method includes: 1) providing a first mask member comprising i) a first pattern unit having a plurality of slits, ii) a first buffer unit spaced apart from the first pattern unit, and iii) a first bonding unit interconnecting the first pattern unit and the first buffer unit and 2) providing a second mask member comprising i) a second pattern unit having a plurality of slits, ii) a second buffer unit spaced apart from the second pattern unit, and iii) a second bonding unit interconnecting the second pattern unit and the second buffer unit. The method may further include contacting the first bonding unit and the second bonding unit; and connecting the first mask member to the second mask member while tensile forces are applied to the first mask member and the second mask member.

Abstract: A flash memory device, including a cell array region where a plurality of memory cells are connected in series to a single cell string, the cell array region including a pocket p-well configured to accommodate the plurality of memory cells and an n-well configured to surround the pocket p-well, a first peripheral region where low-voltage (LV) and high-voltage (HV) switches are connected to the memory cells through a word line, and a second peripheral region where bulk voltage switches are connected to bulk regions of the LV and HV switches.

Abstract: A semiconductor package includes a semiconductor chip including a semiconductor substrate and a plurality of cell transistors arranged on the semiconductor substrate. Channel regions of the cell transistors have channel lengths that extend in a first direction, and the package further includes a supporting substrate having an upper surface on which the semiconductor chip is affixed. The supporting substrate is configured to bend in response to a temperature increase in a manner that applies a tensile stress to the channel regions of the semiconductor chip in the first direction. Related methods are also disclosed.

Abstract: A deposition apparatus that improves deposition characteristics and the uniformity of a deposited layer, and a method of manufacturing an organic light emitting device using the deposition apparatus. The deposition apparatus includes: a base; a heat blocking layer formed on the base; a heat emitting layer patterned into stripes and formed on the heat blocking layer to heat a deposition material to be deposited; and a barrier rib formed and patterned on the heat blocking layer to define a space in which the deposition material is disposed.

Abstract: A thin film deposition apparatus including a deposition source having a crucible to contain a deposition material and a heater to heat and vaporize the deposition material; a nozzle unit disposed at a side of the deposition source along a first direction and having a plurality of nozzle slits to discharge the deposition material that was vaporized; a plurality of emission coefficient increasing units disposed toward the nozzle unit within the deposition source and increasing a quantity of motion of the deposition material that is discharged toward the nozzle unit; a patterning slit sheet disposed opposite to the nozzle unit and having a plurality of patterning slits arranged along the first direction; and a barrier plate assembly disposed between the nozzle unit and the patterning slit sheet along the first direction, and having a plurality of barrier plates that partition a space between the nozzle unit and the patterning slit sheet into a plurality of sub-deposition spaces.

Abstract: A frit sealing system and a method of manufacturing an organic light emitting display device by using the frit sealing system, and more particularly, a frit sealing system and a method of manufacturing an organic light emitting display device by using the frit sealing system, which includes a pressure member so as to physically pressurize a first substrate and a second substrate, thereby increasing adhesion of a frit when the first substrate and the second substrate are adhered to each other by using the frit.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate.

Abstract: In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.