Abstract: A thin film deposition apparatus that can be simply applied to manufacture a thin film on a large substrate on a mass scale and that improves manufacturing yield includes a deposition source; a first nozzle disposed at a side of the deposition source and including first slits arranged in a first direction; a second nozzle assembly disposed opposite to the deposition source and including strings arranged in the first direction; and a barrier wall assembly including barrier walls disposed between the first nozzle and the second nozzle assembly to partition a space between the first nozzle and the second nozzle assembly into a plurality of sub-deposition spaces. The second nozzle assembly is movable relative to the target along a plane parallel to a surface of the target, or the target is movable relative to the second nozzle along the plane.

Abstract: A thin film deposition apparatus that can be used to manufacture large substrates on a mass scale and that improves manufacturing yield, and an organic light-emitting display device manufactured using the thin film deposition apparatus.

Abstract: A thin film deposition apparatus and a method of manufacturing an organic light emitting device (OLED) using the thin film deposition apparatus.

Abstract: A thin film deposition apparatus that can be simply applied to produce large substrates on a mass scale and that improves manufacturing yield includes a deposition source; a first nozzle that is disposed at a side of the deposition source and includes a plurality of first slits arranged in a first direction; a second nozzle that is disposed opposite to the first nozzle and includes second slits arranged in the first direction; and a barrier wall assembly that is disposed between the first nozzle and the second nozzle in the first direction, and includes barrier walls that partition a space between the first nozzle and the second nozzle into sub-deposition spaces. A distance between the adjacent second slits is different.

Abstract: A thin film deposition apparatus capable of forming a precise deposition pattern on a large substrate includes a deposition source; a first nozzle disposed at a side of the deposition source having a plurality of first slits; a second nozzle disposed opposite to the first nozzle having a plurality of second slits; and a second nozzle frame bound to the second nozzle so as to support the second nozzle. The second nozzle frame includes two first frame portions spaced apart from each other and disposed in a direction in which the plurality of second slits are arranged, and two second frame portions each connecting the two first frame portions to each other, wherein the second frame portions are curved in the direction in which the plurality of second slits are arranged, so as to form arches.

Abstract: A method of cleaning off organic deposition material accumulated on a mask includes forming an organic deposition material pattern on a substrate using the mask, which includes a plurality of slots, in a deposition chamber including a deposition source; transporting the mask to a stock chamber that is maintained at a vacuum and adjacent to the deposition chamber; and partially cleaning off the organic deposition material accumulated along the boundaries of the slots of the mask in the stock chamber. A system to clean off an organic deposition material accumulated on a mask having a plurality of slots, includes a deposition chamber including a deposition source; and a stock chamber that is maintained at substantially the same vacuum as the deposition chamber and includes a cleaning device that cleans off the organic deposition material accumulated on the mask.

Abstract: A thin film deposition apparatus to form a fine pattern on a large substrate. The thin film deposition apparatus includes a deposition source, a first nozzle that is disposed at a side of the deposition source and includes a plurality of first slits, a second nozzle that is disposed opposite to the deposition source and includes a plurality of second slits, and a second nozzle reinforcement unit that is disposed on the second nozzle and crosses the second nozzle.

Abstract: In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics.

Abstract: A thin film deposition apparatus that can be simply applied to manufacture large-sized display devices on a mass scale and that improves manufacturing yield includes: a deposition source; a first nozzle disposed at a side of the deposition source and including a plurality of first slits arranged in a first direction; a second nozzle disposed opposite to the first nozzle and including a plurality of second slits arranged in the first direction; a barrier wall assembly including a plurality of barrier walls that are arranged in the first direction in order to partition a space between the first nozzle and the second nozzle; and an alignment member including an interval control member that adjusts an interval between the second nozzle and the substrate, and/or an alignment control member that adjusts alignment between the second nozzle and the substrate.

Abstract: Coupling among adjacent rows of memory cells on an integrated circuit substrate may reduced by forming the adjacent rows of memory cells on adjacent semiconductor pedestals that extend different distances away from the integrated circuit substrate. NAND flash memory devices that include different pedestal heights and fabrication methods for integrated circuit memory devices are also disclosed.

Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

Abstract: Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

Abstract: An hermetic sealing apparatus is discussed. The apparatus may include one or more of the following a glass mask disposed on an upper surface of a first substrate, a support member disposed on an upper surface of the glass mask, a laser irradiation member positioned spaced on the upper surface of the glass mask, a plurality of lower support members disposed in a contour region of a lower surface of the second substrate, and pressing members disposed on a lower surface of the lower support members.

Abstract: In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first opening in the mask layer to expose a first gate region in the cell area of the semiconductor substrate, and then forming a FinFET gate electrode in the first opening using a damascene process. A MOSFET gate fabricated by forming a second opening in the mask layer to expose a second gate region in the peripheral circuit area of the semiconductor substrate, and then forming a MOSFET gate electrode in the second opening using a damascene process.

Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

Abstract: A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin. A dielectric layer may be formed on the floating gate so that the floating gate is between the dielectric layer and the fin, and a control gate electrode may be formed on the dielectric layer so that the dielectric layer is between the control gate and the fin. Related devices are also discussed.

Abstract: A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of multiple memory strings, and each including a control gate and a charge storage layer. Multiple common bit lines are each commonly connected to ends of each of one pair of memory strings among the memory strings. Provided are a first selection transistor having a first driving voltage and multiple second selection transistors connected in series to the first selection transistors and having a second driving voltage that is lower than the first driving voltage. The first selection transistor and the second selection transistors are arranged between the common bit lines and the unit elements of the of memory strings. A first string selection line is connected to one of the first and second selection transistors of a first memory string of one pair of memory strings that are connected to one of the common bit lines.

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.