Abstract: A semiconductor device includes a semiconductor channel region and a gate region, wherein the gate region includes at least one buried part extending under the channel region. The buried part of the gate region is formed from a cavity under the channel region. The cavity is filled with a first material. An opening is made to access the first material. In one implementation, aluminium is deposited in the opening in contact with the first material. An anneal is performed to cause the aluminium to be substituted for the first material in the cavity. In another implementation, a second material different from the first material is deposited in the opening. An anneal is performed to cause an alloy of the first and second materials to be formed in the cavity.

Abstract: A semiconductor device includes a semiconductor channel region and a gate region, wherein the gate region includes at least one buried part extending under the channel region. The buried part of the gate region is formed from a cavity under the channel region. The cavity is filled with a first material. An opening is made to access the first material. In one implementation, aluminum is deposited in the opening in contact with the first material. An anneal is performed to cause the aluminum to be substituted for the first material in the cavity. In another implementation, a second material different from the first material is deposited in the opening. An anneal is performed to cause an alloy of the first and second materials to be formed in the cavity.

Abstract: A process for fabricating a transistor that includes a gate located in the immediate proximity of a dielectric includes a step of etching a layer of gate material. The gate etching step includes plasma etching of the gate layer over the major portion of its thickness so as to laterally define the gate and chemical etching of a residual portion of the gate layer so as to define the gate as far as the dielectric.

Abstract: A process for fabricating a transistor comprising a gate (50?) located in the immediate proximity of a dielectric (46) includes a step of etching a layer of gate material. This gate etching step comprises the following steps: plasma etching of this layer over the major portion of its thickness so as to laterally define the gate (50?); chemical etching of a residual portion (48?) of this layer so as to define this gate as far as the dielectric (46).