Patents by Inventor Christine Dehm

Christine Dehm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7746683
    Abstract: A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: June 29, 2010
    Assignee: Qimonda AG
    Inventors: Kurt Hoffmann, Christine Dehm, Recai Sezi, Andreas Walter
  • Publication number: 20080099756
    Abstract: An integrated semiconductor memory with a cell array is disclosed. In one embodiment the memory includes a multiplicity of memory cells arranged in rows and columns. In at least one memory cell, an organic selection transistor is integrated in a stack arrangement above an organic storage element.
    Type: Application
    Filed: May 30, 2005
    Publication date: May 1, 2008
    Inventors: Hagen Klauk, Marcus Halik, Ute Zschieschang, Guenter Schmid, Christine Dehm
  • Publication number: 20070242496
    Abstract: A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.
    Type: Application
    Filed: April 19, 2007
    Publication date: October 18, 2007
    Applicant: QIMONDA AG
    Inventors: Kurt Hoffmann, Christine Dehm, Recai Sezi, Andreas Walter
  • Publication number: 20070194301
    Abstract: One aspect of the invention relates to a semiconductor arrangement having at least one nonvolatile memory cell which has a first electrode comprising at least two layers; and having an organic material, the organic material forming a compound with that layer of the first electrode which is in direct contact. One aspect of the invention furthermore relates to a method for producing the nonvolatile memory cell, a semiconductor arrangement having a plurality of memory cells according to the invention, and a method for producing the same.
    Type: Application
    Filed: November 24, 2004
    Publication date: August 23, 2007
    Inventors: Recai Sezi, Andreas Walter, Reimund Engl, Anna Maltenberger, Christine Dehm, Sitaram Arkalgud, Igor Kasko, Joachim Nuetzel, Jakob Kriz, Thomas Mikolajick, Cay-Uwe Pinnow
  • Patent number: 7115897
    Abstract: A semiconductor circuit configuration has at least one pair of complementary operating field-effect transistors in which each transistor has a gate region, first and second source/drain regions and also a channel region with or made of an organic semiconductor material that is provided in between. It is furthermore provided that the gate regions are formed such that they are electrically coupled to one another via a capacitor configuration.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: October 3, 2006
    Assignee: Infineon Technologies AG
    Inventors: Günter Schmid, Marcus Halik, Hagen Klauk, Christine Dehm, Thomas Haneder, Thomas Mikolajick
  • Patent number: 7049628
    Abstract: The semiconductor memory cell is characterized in that at least one modulation region is provided between a first gate electrode of the gate electrode configuration and the insulation region, and in that the modulation region has or is formed from a material or modulation material having electrical and/or further material properties that can be modulated in a controllable manner between at least two states in such a way that, in accordance with these states of the modulation material or of the modulation region, the channel region can be influenced electromagnetically, in particular for a given electrical potential difference between the first gate electrode and the source/drain regions.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: May 23, 2006
    Assignee: Infineon Technologies AG
    Inventors: Günter Schmid, Marcus Halik, Hagen Klauk, Christine Dehm, Thomas Haneder, Thomas Mikolajick
  • Patent number: 7005303
    Abstract: A low temperature CVD process for deposition of bismuth-containing ceramic thin films suitable for integration to fabricate ferroelectric memory devices. The bismuth-containing film can be formed using a tris(?-diketonate) bismuth precursor. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: February 28, 2006
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Frank S. Hintermaier, Christine Dehm, Wolfgang Hoenlein, Peter C. Van Buskirk, Jeffrey F. Roeder, Bryan C. Hendrix, Thomas H. Baum, Debra A. Desrochers
  • Patent number: 6958501
    Abstract: A continuous contact hole is formed in an insulation layer that separates a storage capacitor from a switching transistor. All except a section of the contact hole is filled with poly-Si. A conductive, oxidizable interlayer and a conductive oxygen barrier layer are deposited on the Poly-Si in the remaining section of the contact hole such that the interlayer is completely surrounded by the poly-Si of the contact hole, the insulation layer, and the barrier layer.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: October 25, 2005
    Assignee: Infineon Technologies AG
    Inventors: Arkalgud Sitaram, Christine Dehm, Carlos Mazuré-Espejo
  • Patent number: 6844581
    Abstract: A storage capacitor, in particular a ferroelectric or paraelectric storage capacitor, and an associated contact-making structure are formed in such a way that the storage capacitor has a first electrode layer, a second electrode layer and a dielectric, ferroelectric or paraelectric capacitor intermediate layer. Proceeding from the plane of the surface of the insulation layer, the storage capacitor extends at least partly into the interior of the via contact and is electrically connected to the via contact.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: January 18, 2005
    Assignee: Infineon Technologies AG
    Inventors: Arkalgud Sitaram, Christine Dehm, Carlos Mazuré-Espejo
  • Publication number: 20040209384
    Abstract: A low temperature CVD process for deposition of bismuth-containing ceramic thin films suitable for integration to fabricate ferroelectric memory devices. The bismuth-containing film can be formed using a tris(&bgr;-diketonate) bismuth precursor. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.
    Type: Application
    Filed: April 30, 2004
    Publication date: October 21, 2004
    Inventors: Frank S. Hintermaier, Christine Dehm, Wolfgang Hoenlein, Peter C. Van Buskirk, Jeffrey F. Roeder, Bryan C. Hendrix, Thomas H. Baum, Debra A. Desrochers
  • Patent number: 6787832
    Abstract: A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region that includes or is made of an organic semiconductor material. Besides a first gate electrode of the gate electrode configuration of the field-effect transistor device, an additional selection gate electrode is provided, by way of which the field-effect transistor device can be switched off without influencing the storage dielectric and independently of the first gate electrode.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: September 7, 2004
    Assignee: Infineon Technologies AG
    Inventors: Günter Schmid, Marcus Halik, Hagen Klauk, Christine Dehm, Thomas Haneder, Thomas Mikolajick
  • Patent number: 6730523
    Abstract: A low temperature CVD process using a tris (&bgr;-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: May 4, 2004
    Assignees: Advanced Technology Materials, Inc., Siemens Aktiengesellschaft
    Inventors: Frank S. Hintermaier, Christine Dehm, Wolfgang Hoenlein, Peter C. Van Buskirk, Jeffrey F. Roeder, Bryan C. Hendrix, Thomas H. Baum, Debra A. Desrochers
  • Patent number: 6670662
    Abstract: The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions and has a lower oxide layer arranged on a silicon substrate and an upper oxide layer arranged on the lower oxide layer, each memory cell comprising at least one transistor in the transition region between silicon substrate and lower oxide layer and a capacitor in the transition region between lower oxide layer and upper oxide layer, which capacitor is connected to the transistor via a contact hole, which is filled with metal, in the lower oxide layer and comprises a ferroelectric arranged between two electrodes, the electrode which is connected to the transistor and adjoins the lower oxide layer having a relatively great thickness, and each logic region comprising at least one transistor in the transition region between silicon substrate and lower oxide layer, which transistor is connected to an electrode on the topside of the upper oxide layer via a c
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: December 30, 2003
    Assignee: Infineon Technologies, AG
    Inventors: Christine Dehm, Guenther Schindler
  • Publication number: 20030234397
    Abstract: The semiconductor memory cell is characterized in that at least one modulation region is provided between a first gate electrode of the gate electrode configuration and the insulation region, and in that the modulation region has or is formed from a material or modulation material having electrical and/or further material properties that can be modulated in a controllable manner between at least two states in such a way that, in accordance with these states of the modulation material or of the modulation region, the channel region can be influenced electromagnetically, in particular for a given electrical potential difference between the first gate electrode and the source/drain regions.
    Type: Application
    Filed: March 24, 2003
    Publication date: December 25, 2003
    Inventors: Gunter Schmid, Marcus Halik, Hagen Klauk, Christine Dehm, Thomas Haneder, Thomas Mikolajick
  • Publication number: 20030234428
    Abstract: A semiconductor circuit configuration has at least one pair of complementary operating field-effect transistors in which each transistor has a gate region, first and second source/drain regions and also a channel region with or made of an organic semiconductor material that is provided in between. It is furthermore provided that the gate regions are formed such that they are electrically coupled to one another via a capacitor configuration.
    Type: Application
    Filed: March 24, 2003
    Publication date: December 25, 2003
    Inventors: Gunter Schmid, Marcus Halik, Hagen Klauk, Christine Dehm, Thomas Haneder, Thomas Mikolajick
  • Patent number: 6664158
    Abstract: An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged using the stacking principle, and both capacitor electrodes, which are located one above the other, of each memory cell are directly electrically connected by means of contact plugs to corresponding source and drain regions of an associated selection transistor in the substrate. Contact plugs for the contact connection to the upper capacitor electrodes are produced from above the configuration.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: December 16, 2003
    Assignee: Infineon Technologies AG
    Inventors: Christine Dehm, Heinz Hönigschmid, Thomas Röhr
  • Patent number: 6656376
    Abstract: A cleaning process for cleaning CVD units is disclosed. In the cleaning process, alkaline earth metal and/or metal-containing process residues, which form an amorphous film on reactor walls, are removed using a dry etching medium containing free diketones at a greatly reduced pressure and an elevated temperature. In the process, the free diketones react with the alkaline earth metals or metals to form volatile complexes.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: December 2, 2003
    Assignee: Siemens Aktiengesellschaft
    Inventors: Elke Fritsch, Christine Dehm, Hermann Wendt, Volker Weinrich
  • Publication number: 20030178660
    Abstract: A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region the includes or is made of an organic semiconductor material. Besides a first gate electrode of the gate electrode configuration of the field-effect transistor device, an additional selection gate electrode is provided, by way of which the field-effect transistor device can be switched off without influencing the storage dielectric and independently of the first gate electrode.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 25, 2003
    Inventors: Gunter Schmid, Marcus Halik, Hagen Klauk, Christine Dehm, Thomas Haneder, Thomas Mikolajick
  • Patent number: 6559003
    Abstract: A method of producing a ferroelectric semiconductor memory, includes forming a switching transistor on a semiconductor substrate, applying an insulating layer to the switching transistor and then forming a storage capacitor, with electrodes of platinum and a ferroelectric or paraelectric dielectric, on the insulating layer. In order to protect the dielectric from being penetrated by hydrogen during further process steps, a first barrier layer is embedded into the insulating layer and, after completion of the storage capacitor, a second barrier layer, which bonds with the first barrier layer, is deposited.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: May 6, 2003
    Assignee: Infineon Technologies AG
    Inventors: Walter Hartner, Günther Schindler, Marcus Kastner, Christine Dehm
  • Patent number: 6500677
    Abstract: The invention provides a method. In a first step of a method for fabricating a ferroelectric memory configuration, there is provided a substrate having a multiplicity of memory cells. Each of the memory cells has at least one select transistor, at least one short-circuit transistor, and at least one ferroelectric capacitor. The transistors are connected in an electrically conductive manner to a first of the electrodes of the ferroelectric capacitor. In the next step, at least one electrically insulating layer is applied. In the next step, at least one contact hole for connecting a second electrode of the ferroelectric capacitors is produced. Next, contact holes for connecting the short-circuit transistors are produced. Next, the contact holes are filled with electrically conductive material. Next, an electrically conductive layer is applied and patterned, so that the second electrodes of the ferroelectric capacitors are each conductively connected to the short-circuit transistors.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: December 31, 2002
    Assignee: Infineon Technologies AG
    Inventors: Renate Bergmann, Christine Dehm, Thomas Roehr, Georg Braun, Heinz Hoenigschmid, Günther Schindler