Abstract: An integrated circuit including solder balls containing an elastic or resilient material core, a hard or rigid shell substantially enclosing the core, and an electrical contact layer substantially enclosing the shell. The elastic or resilient core serves as a stress buffer layer in a wafer level package (WLP) integrated circuit. The elastic or resilient material core may include an organic plastic material, such as a Divinilbenzene cross-linked co-polymer of relatively high resistance. This material has a relatively good elongation property so that it can effectively absorb forces exerted upon the integrated circuit by, for example, the flexing of a printed circuit board (PCB) or other structure to which the integrated circuit is attached. The hard or rigid shell serves to contain the elastic or resilient core and may include copper. The electrical contact layer serve to provide a good adhesive electrical contact to an under bump metallization (UBM) layer, may include a lead free, Tin-Gold (SnAg) material.

Abstract: A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (303, preferably silicon nitride) on the chip surface, followed by a polymer layer (306, preferably benzocyclobutene) on the first inorganic layer (303), and finally an outermost second inorganic layer (310, preferably silicon dioxide) on the polymer layer (303). A window (301a) in the stack of layers exposes the metallization (301) of the IC. A patterned seed metal layer (307, preferably copper) is on the metallization (301) in the window and on the second inorganic layer (310) around the window. A buffer metal layer (308, preferably copper) is positioned on the seed metal layer (307). A metal reflow element (309) is attached to the buffer metal (308).

Abstract: A metal structure (600) for a bonding pad on integrated circuit wafers, which have interconnecting metallization (101) protected by an insulating layer (102) and selectively exposed by windows in the insulating layer. The structure comprises a patterned seed metal layer (104) positioned on the interconnecting metallization exposed by the window so that the seed metal establishes ohmic contact to the metallization as well as a practically impenetrable seal of the interface between the seed metal and the insulating layer. Further, a metal stud (301) is formed on the seed metal and aligned with the window. The metal stud is conformally covered by a barrier metal layer (501) and an outermost bondable metal layer (502).

Abstract: A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (303, preferably silicon nitride) on the chip surface, followed by a polymer layer (306, preferably benzocyclobutene) on the first inorganic layer (303), and finally an outermost second inorganic layer (310, preferably silicon dioxide) on the polymer layer (303). A window (301a) in the stack of layers exposes the metallization (301) of the IC. A patterned seed metal layer (307, preferably copper) is on the metallization (301) in the window and on the second inorganic layer (310) around the window. A buffer metal layer (308, preferably copper) is positioned on the seed metal layer (307). A metal reflow element (309) is attached to the buffer metal (308).

Abstract: A method for preparing a bonding pad on an integrated circuit wafer by the steps of depositing a conductive seed layer (104) on the bonding pad; depositing a metal layer (301, 302, and 303) over a portion of the conductive seed layer; and immersing the wafer in an etchant solution (501) to remove the portion of the seed layer not covered by the metal layer. The etchant solution contains a chelating agent that bonds ions from the seed layer. When the seed layer is copper or a refractory metal, and the metal layer is gold or palladium, the preferred chelating agent is selected from, but is not limited to, but is not limited to, the families of ethylenediaminetetraacetic acids (EDTA), 8-hydroxy-quinolines, including 8-hydroxy-quinoline-5-sulfonic acid, porphyrins, and phthalocyanines.

Abstract: A metal structure (600) for a bonding pad on integrated circuit wafers, which have interconnecting metallization (101) protected by an insulating layer (102) and selectively exposed by windows in the insulating layer. The structure comprises a patterned seed metal layer (104) positioned on the interconnecting metallization exposed by the window so that the seed metal establishes ohmic contact to the metallization as well as a practically impenetrable seal of the interface between the seed metal and the insulating layer. Further, a metal stud (301) is formed on the seed metal and aligned with the window. The metal stud is conformally covered by a barrier metal layer (501) and an outermost bondable metal layer (502).

Abstract: A structure and a fabrication method for metallurgical connections between solder bumps and contact pads positioned on integrated circuits (IC) having copper interconnecting metallization protected by an overcoat. The structure comprises a portion of the copper metallization exposed by a window in the overcoat, where the exposed copper has a chemically and plasma cleaned surface. A copper layer is directly positioned on the clean copper metallization, and patterned; the resulting metal structure has an electrical (and thermal) conductivity about equal to the conductivity of pure copper. The copper layer overlaps the perimeter of the overcoat window and a copper stud is positioned on said copper layer. Finally, one of the solder bumps is bonded to the copper stud.

Abstract: According to one embodiment of the present invention, a method for electroplating electronic devices is disclosed which includes placing the outer surface of a substrate in contact with a solution comprising a conductive material. An electrical current is passed through the solution and the substrate so as to cause the conductive material to deposit on the substrate under the electromotive force caused by the electrical current. The level of the electrical current is varied from a first current level to a second current level to provide for differing rates of deposition of the conductive material on the substrate. The second current level provides a relaxation period to allow the conductive material deposited on the substrate to come to equilibrium.

Abstract: A structure and a fabrication method for metallurgical connections between solder bumps and contact pads positioned on integrated circuits (IC) having copper interconnecting metallization protected by an overcoat. The structure comprises a portion of the copper metallization exposed by a window in the overcoat, where the exposed copper has a chemically and plasma cleaned surface. A copper layer is directly positioned on the clean copper metallization, and patterned; the resulting metal structure has an electrical (and thermal) conductivity about equal to the conductivity of pure copper. The copper layer overlaps the perimeter of the overcoat window and a copper stud is positioned on said copper layer. Finally, one of the solder bumps is bonded to the copper stud.

Abstract: A microelectronic mechanical structure (MEMS) comprising a semiconductor chip having an integrated circuit including a plurality of micromechanical components, and a plurality of conductive routing lines integral with the chip; the routing lines having contact terminals of oxide-free metal; and the terminals having a layer of barrier metal on the oxide-free metal and an outermost layer of noble metal, whereby damage-free testing of the circuit is possible using test probe needles.

Abstract: A pulsed lamp is supplied wherein electrons are supplied from a substantially flat cold cathode having low effective field emission work function and are accelerated to excite light emission from a phosphor layer on a transparent anode plate. The emission site density of the cathode and emission current characteristics vs electric field are selected to provide high light output while requiring only small duty cycle pulses from a voltage generator.

Abstract: A cathode assembly includes a substrate (1101), a plurality of electrically conductive strips (1102), nano-size diamond particles (1701), and a layer (1801) of diamond material deposited (CVD) over the diamond particles (1701).

Abstract: The present invention provides for a field emission device including an anode assembly and a cathode assembly, wherein the cathode assembly further includes a substrate, a plurality of electrically conducting strips deposited on the substrate, and a continuous layer of diamond material deposited over the plurality of electrically conducting strips and portions of the substrate exposed between the plurality of electrically conducting strips. The field emission device may further include a grid assembly including a perforated silicon substrate, a first dielectric layer deposited on the silicon substrate, and a first conducting layer deposited on the first dielectric layer, wherein the first dielectric layer and the first conducting layer have perforations coinciding with perforations of the silicon substrate.

Abstract: A cathode assembly includes a substrate, a plurality of electrically conducting strips deposited on the substrate, and a continuous layer of diamond material deposited over the plurality of electrically conducting strips and portions of the substrate exposed between the plurality of electrically conducting strips.