Patents by Inventor Christoph Kadow

Christoph Kadow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10615029
    Abstract: A method for manufacturing a device includes: providing a semiconductor substrate having an RF-device; providing a BEOL-layer stack on the first main surface of the semiconductor substrate; attaching a carrier structure to a first main surface of the BEOL-layer stack; removing a lateral portion of the semiconductor substrate which laterally adjoins the device region to expose a lateral portion of the second main surface of the BEOL-layer stack; and opening a contacting region of the BEOL-layer stack at the lateral portion of second main surface of the BEOL-layer stack.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: April 7, 2020
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kadow, Uwe Seidel
  • Patent number: 10522675
    Abstract: An integrated circuit includes a first and a second field effect transistor structure. The first field effect transistor structure includes a first gate electrode structure and a first field electrode structure. The second field effect transistor structure includes a second gate electrode structure and a second field electrode structure. The first and the second gate electrode structures are electrically separated from each other. The first and the second field electrode structures are separated from each other.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: December 31, 2019
    Assignee: Infineon Technologies AG
    Inventor: Christoph Kadow
  • Publication number: 20190043716
    Abstract: A method for manufacturing a device includes: providing a semiconductor substrate having an RF-device; providing a BEOL-layer stack on the first main surface of the semiconductor substrate; attaching a carrier structure to a first main surface of the BEOL-layer stack; removing a lateral portion of the semiconductor substrate which laterally adjoins the device region to expose a lateral portion of the second main surface of the BEOL-layer stack; and opening a contacting region of the BEOL-layer stack at the lateral portion of second main surface of the BEOL-layer stack.
    Type: Application
    Filed: July 24, 2018
    Publication date: February 7, 2019
    Inventors: Christoph Kadow, Uwe Seidel
  • Patent number: 9865792
    Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 9, 2018
    Assignee: Infineon Technologies AG
    Inventors: Donald Dibra, Christoph Kadow, Markus Zundel
  • Patent number: 9761665
    Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: September 12, 2017
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Stefan Decker, Norbert Krischke, Christoph Kadow
  • Publication number: 20170154965
    Abstract: A semiconductor device includes a semiconductor substrate including, between a bottom side and a top side, a first trench and a second trench extending in a vertical direction, and a contact groove arranged between the first trench and the second trench. The contact groove has a longitudinal extension in a plane perpendicular to the vertical direction. The longitudinal extension of the contact groove at least partially has a wave-shape.
    Type: Application
    Filed: November 25, 2016
    Publication date: June 1, 2017
    Inventors: Ralf Siemieniec, Oliver Blank, Marion Hoja, Christoph Kadow, Sabine Konrad, Cedric Ouvrard
  • Patent number: 9646855
    Abstract: Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1?0, y1?0, z1?0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2?0, z2?0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Walter Rieger, Christoph Kadow, Markus Zundel
  • Patent number: 9614033
    Abstract: An embodiment of a semiconductor device comprises a first load terminal contact area at a first side of a semiconductor body. A second load terminal contact area is at a second side of the semiconductor body opposite to the first side. A control terminal contact area is at the second side of the semiconductor body. An isolation structure extends through the semiconductor body between the first and second sides. The isolation structure electrically isolates a first part of the semiconductor body from a second part of the semiconductor body. A first thickness of the first part of the semiconductor body is smaller than a second thickness of the second part of the semiconductor body.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: April 4, 2017
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kadow, Till Schloesser
  • Patent number: 9564425
    Abstract: An integrated transistor structure includes an epitaxial layer on a semiconductor substrate, a power transistor formed in a first region of the epitaxial layer and having a drain region, a source region and a body region shorted to the source region, a bipolar transistor formed in a second region of the epitaxial layer spaced apart from the power transistor. A first trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the power transistor includes a gate electrode spaced apart from a channel region of the power transistor by an insulating material. A second trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor includes a trench electrode spaced apart from the epitaxial layer by an insulating material. The gate electrode, base and emitter of the bipolar transistor are connected to different contacts isolated from one another.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: February 7, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Christoph Kadow, Thorsten Meyer, Norbert Krischke
  • Patent number: 9450019
    Abstract: A power semiconductor device includes a semiconductor body including a first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area including at least one of several transistor structures connected in parallel and several diode structures connected in parallel, and a peripheral area arranged between the active area and the edge. The power semiconductor further device includes a plurality of word lines, a plurality of bit lines separated from the word lines, and a plurality of temperature sensors arranged on or at the first surface, wherein each of the temperature sensors is connected with one of the bit lines and one of the word lines or each of the temperature sensors is formed by a respective portion of one of the bit lines.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kadow, Marc Strasser
  • Publication number: 20160260803
    Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
    Type: Application
    Filed: May 18, 2016
    Publication date: September 8, 2016
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Meyer, Stefan Decker, Norbert Krischke, Christoph Kadow
  • Publication number: 20160190241
    Abstract: An embodiment of a semiconductor device comprises a first load terminal contact area at a first side of a semiconductor body. A second load terminal contact area is at a second side of the semiconductor body opposite to the first side. A control terminal contact area is at the second side of the semiconductor body. An isolation structure extends through the semiconductor body between the first and second sides. The isolation structure electrically isolates a first part of the semiconductor body from a second part of the semiconductor body. A first thickness of the first part of the semiconductor body is smaller than a second thickness of the second part of the semiconductor body.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 30, 2016
    Inventors: Christoph Kadow, Till Schloesser
  • Patent number: 9355909
    Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Stefan Decker, Norbert Krischke, Christoph Kadow
  • Patent number: 9299829
    Abstract: A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: March 29, 2016
    Assignee: Infineon Technologies AG
    Inventors: Andreas Peter Meiser, Markus Zundel, Christoph Kadow
  • Publication number: 20150364524
    Abstract: A power semiconductor device includes a semiconductor body including a first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area including at least one of several transistor structures connected in parallel and several diode structures connected in parallel, and a peripheral area arranged between the active area and the edge. The power semiconductor further device includes a plurality of word lines, a plurality of bit lines separated from the word lines, and a plurality of temperature sensors arranged on or at the first surface, wherein each of the temperature sensors is connected with one of the bit lines and one of the word lines or each of the temperature sensors is formed by a respective portion of one of the bit lines.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: Christoph Kadow, Marc Strasser
  • Publication number: 20150311195
    Abstract: An integrated transistor structure includes an epitaxial layer on a semiconductor substrate, a power transistor formed in a first region of the epitaxial layer and having a drain region, a source region and a body region shorted to the source region, a bipolar transistor formed in a second region of the epitaxial layer spaced apart from the power transistor. A first trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the power transistor includes a gate electrode spaced apart from a channel region of the power transistor by an insulating material. A second trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor includes a trench electrode spaced apart from the epitaxial layer by an insulating material. The gate electrode, base and emitter of the bipolar transistor are connected to different contacts isolated from one another.
    Type: Application
    Filed: July 6, 2015
    Publication date: October 29, 2015
    Inventors: Christoph Kadow, Thorsten Meyer, Norbert Krischke
  • Publication number: 20150249020
    Abstract: Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1?0, y1?0, z1?0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2?0, z2?0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.
    Type: Application
    Filed: May 13, 2015
    Publication date: September 3, 2015
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Oliver Haeberlen, Walter Rieger, Christoph Kadow, Markus Zundel
  • Patent number: 9112021
    Abstract: A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 18, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Christoph Kadow, Thorsten Meyer, Norbert Krischke
  • Patent number: 9105470
    Abstract: A switching component includes a control element and an integrated circuit. The integrated circuit includes a first transistor element and a second transistor element electrically connected in parallel to the first transistor element. The first transistor element includes first transistors, gate electrodes of which are disposed in first trenches in a first main surface of a semiconductor substrate. The second transistor element includes second transistors, gate electrodes of which are disposed in second trenches in the first main surface, and a second gate conductive line in contact with the gate electrodes in the second trenches. The control element is configured to control a potential applied to the second gate conductive line.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: August 11, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Noebauer, Christoph Kadow, Donald Dibra, Robert Illing
  • Publication number: 20150214357
    Abstract: A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode.
    Type: Application
    Filed: April 9, 2015
    Publication date: July 30, 2015
    Inventors: Andreas Peter Meiser, Markus Zundel, Christoph Kadow