Patents by Inventor Christoph Kadow

Christoph Kadow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120012924
    Abstract: A vertical transistor component is produced by providing a semiconductor body with a first surface and a second surface, producing at least one gate contact electrode in a trench, the trench extending from the first surface through the semiconductor body to the second surface, and producing at least one gate electrode connected to the at least one gate contact electrode in the region of the first surface.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 19, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Andreas Peter MEISER, Markus ZUNDEL, Christoph KADOW
  • Patent number: 8097918
    Abstract: A semiconductor arrangement including a load transistor and a sense transistor that are integrated in a semiconductor body. One embodiment provides a number of transistor cells integrated in the semiconductor body, each transistor cell including a first active transistor region. A number of first contact electrodes, each of the contact electrodes contacting the first active transistor regions through contact plugs. A second contact electrode contacts a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes. The transistor cells being contacted by first contact electrodes of the first group form a load transistor, with the second electrode forming a load terminal of the load transistor. The transistor cells being contacted by first contact electrodes of the second group form a sense transistor.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: January 17, 2012
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kadow, Markus Leicht, Stefan Woehlert
  • Publication number: 20120007176
    Abstract: A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 12, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Christoph KADOW, Thorsten MEYER, Norbert KRISCHKE
  • Patent number: 8084821
    Abstract: An integrated circuit includes a first transistor having a first gate and a first source and a second transistor having a second gate and a second source. The integrated circuit includes a first source contact adjacent the second transistor and coupled to the first source and the second source. The integrated circuit includes a first bond wire coupled to the first source contact.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: December 27, 2011
    Assignee: Infineon Technologies AG
    Inventors: Donald Dibra, Christoph Kadow
  • Publication number: 20110147796
    Abstract: Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1?0, y1?0, z1?0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2?0, z2?0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Oliver Haeberlen, Walter Rieger, Christoph Kadow, Markus Zundel
  • Publication number: 20110037126
    Abstract: A semiconductor arrangement including a load transistor and a sense transistor that are integrated in a semiconductor body. One embodiment provides a number of transistor cells integrated in the semiconductor body, each transistor cell including a first active transistor region. A number of first contact electrodes, each of the contact electrodes contacting the first active transistor regions through contact plugs. A second contact electrode contacts a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes. The transistor cells being contacted by first contact electrodes of the first group form a load transistor, with the second electrode forming a load terminal of the load transistor. The transistor cells being contacted by first contact electrodes of the second group form a sense transistor.
    Type: Application
    Filed: August 14, 2009
    Publication date: February 17, 2011
    Applicant: Infineon Technologies AG
    Inventors: Christoph Kadow, Markus Leicht, Stefan Woehlert
  • Patent number: 7868643
    Abstract: An integrated circuit device comprises a first transistor having a gate coupled to an output of a first operational amplifier, a second transistor having a threshold voltage proportional to a threshold voltage of the first transistor, the second transistor having a gate coupled to an inverting input of a second operational amplifier, an output of the second operational amplifier coupled to an inverting input of the first operational amplifier, a first resistor coupled between the second transistor gate and the inverting input of the second operational amplifier, and a second resistor coupled between the output of the second operational amplifier and the inverting input of the second operational amplifier, a ratio of the second resistor to the first resistor selected based upon a ratio of a production distribution of a transistor source voltage offset to a production distribution of a transistor threshold voltage mismatch.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: January 11, 2011
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kadow, Paolo Del Croce
  • Publication number: 20100270620
    Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.
    Type: Application
    Filed: April 28, 2009
    Publication date: October 28, 2010
    Inventors: Donald Dibra, Christoph Kadow, Markus Zundel
  • Publication number: 20100230764
    Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
    Type: Application
    Filed: March 12, 2009
    Publication date: September 16, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thorsten Meyer, Stefan Decker, Norbert Krischke, Christoph Kadow
  • Publication number: 20100102845
    Abstract: An integrated circuit device comprises a first transistor having a gate coupled to an output of a first operational amplifier, a second transistor having a threshold voltage proportional to a threshold voltage of the first transistor, the second transistor having a gate coupled to an inverting input of a second operational amplifier, an output of the second operational amplifier coupled to an inverting input of the first operational amplifier, a first resistor coupled between the second transistor gate and the inverting input of the second operational amplifier, and a second resistor coupled between the output of the second operational amplifier and the inverting input of the second operational amplifier, a ratio of the second resistor to the first resistor selected based upon a ratio of a production distribution of a transistor source voltage offset to a production distribution of a transistor threshold voltage mismatch.
    Type: Application
    Filed: October 29, 2008
    Publication date: April 29, 2010
    Inventors: Christoph Kadow, Paolo Del Croce
  • Publication number: 20090189461
    Abstract: An integrated circuit includes a first transistor having a first gate and a first source and a second transistor having a second gate and a second source. The integrated circuit includes a first source contact adjacent the second transistor and coupled to the first source and the second source. The integrated circuit includes a first bond wire coupled to the first source contact.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Applicant: Infineon Technologies AG
    Inventors: Donald Dibra, Christoph Kadow
  • Publication number: 20090051405
    Abstract: A circuit includes a transistor having a source, drain, a gate, and an electrode structure. A source terminal is coupled to the source. A drain terminal coupled to the drain. Terminals are coupled to the gate and to the electrode structure. A switch is coupled to the source, the gate terminal and the electrode terminal to selectively couple one of the gate and electrode structure to the source. In further embodiments, a second switch is used to selectively couple a resistor between the gate and the source. A method is used to control the switches to keep the transistor in an off state or allow it to switch to an on state.
    Type: Application
    Filed: August 21, 2007
    Publication date: February 26, 2009
    Inventors: Christoph Kadow, Paolo Del Croce
  • Patent number: 7492212
    Abstract: A circuit includes a transistor having a source, drain, a gate, and an electrode structure. A source terminal is coupled to the source. A drain terminal coupled to the drain. Terminals are coupled to the gate and to the electrode structure. A switch is coupled to the source, the gate terminal and the electrode terminal to selectively couple one of the gate and electrode structure to the source. In further embodiments, a second switch is used to selectively couple a resistor between the gate and the source. A method is used to control the switches to keep the transistor in an off state or allow it to switch to an on state.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: February 17, 2009
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kadow, Paolo Del Croce