Abstract: Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an approach that uses bins can speed up the clustering process, thereby allowing the phase shifting to be performed in parallel on multiple computers. Additional efficiencies result if identical clusters are identified and processing time saved so that repeated clusters of shapes only undergo the computationally expensive phase shifter placement and assignment process a single time.

Abstract: The manufacturing of integrated circuits relies on the use of lithography simulation to predict the image of the mask created on the wafer. Such predictions can be used for example to assess the quality of the images, verify the manufacturability of such images, perform using OPC necessary correction of the mask data to achieve images close to the targets, optimize the printing parameters such as the illumination source, or globally optimize the source and the mask to achieve better printability. This disclosure provides a technique based on the association of at least one kernel function per source region or source point. Each kernel function can be directly convoluted with a mask image to create a prediction of the wafer image. As the kernel functions are associated with the source, the source can be easily changed to create new models. The optical system can be fully described by computing the possible kernels for all possible source points and all possible numerical apertures.

Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

Abstract: The manufacturing of integrated circuits relies on the use of lithography simulation to predict the image of the mask created on the wafer. Such predictions can be used for example to assess the quality of the images, verify the manufacturability of such images, perform using OPC necessary correction of the mask data to achieve images close to the targets, optimize the printing parameters such as the illumination source, or globally optimize the source and the mask to achieve better printability. This disclosure provides a technique based on the association of at least one kernel function per source region or source point. Each kernel function can be directly convoluted with a mask image to create a prediction of the wafer image. As the kernel functions are associated with the source, the source can be easily changed to create new models. The optical system can be fully described by computing the possible kernels for all possible source points and all possible numerical apertures.

Abstract: According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Abstract: According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Abstract: In accordance with some embodiments, a method is provided for creating a photolithographic component, comprising: determining a target pattern for a circuit layout, the target pattern comprising target features; identifying a set of periodic target features within the target pattern; calculating a relationship between feature and pitch for the set of periodic target features; and determining a mask pattern from the target pattern using the relationship, wherein the mask pattern has a set of periodic mask features configured to result in projection of a first subset of the set of periodic target features when exposed to a light source that induces a first phase effect, and configured to result in projection of a second subset of the set of periodic target features when exposed to a light source that induces a second phase effect. In further embodiments, the method outputs the mask pattern as a mask dataset.

Abstract: Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the tilled pattern to remove portions of the final material beyond dimensions of the layout elements.

Abstract: Various systems and methods related to semiconductor devices having a plurality of layers and having a first conductive trace on a first layer electrically connected to a second conductive trace on a second layer and electrically isolated from a third electrical trace on the second layer are provided. A semiconductor structure can include first, second and third layers. The first conducting layer may be etched to form a first trench for the first conductive trace. A layer of material on the second layer in the first trench can define a patch area, wherein the patch area is disposed in a location where the first trench crosses over the third electrical trace. A second trench may be etched in an area defined by the first trench and the patch area to remove material in the second layer exposed by the first trench, leaving material of the layer under the patch area.

Abstract: A semiconductor device and systems and methods for forming a semiconductor device are provided. A method of manufacturing a semiconductor device can include patterning a first conductive element on a first layer of a semiconductor device, patterning a second conductive element on a second layer of a semiconductor device, and forming an electrical connection in a third layer of the semiconductor device at a predetermined location between the first and the second conductive elements, the connection between the first and the second conducting elements having a geometry that is larger in at least one dimension relative to the corresponding dimension of the second conductive element at the predetermined location.

Abstract: According to various embodiments of the invention, systems and methods are provided for compressed design phase contour data created during the manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a contour layout from a target layout during the design phase of a circuit. This contour layout is generated by way of a contour generator tool. Next, a set of differences between the contour layout and the target layout are calculated. A dataset containing these differences is generated. In some embodiments, the contour generator uses a post-optical proximity correction (OPC) layout of the target layout in order to generate the contour layout.

Abstract: Improvements in the fabrication of integrated circuits are driven by the decrease of the size of the features printed on the wafers. Current lithography techniques limits have been extended through the use of phase-shifting masks, off-axis illumination, and proximity effect correction. More recently, liquid immersion lithography has been proposed as a way to extend even further the limits of optical lithography. This invention described a methodology based on contact or proximity printing using a projection lens to define the image of the mask onto the wafer. As the imaging is performed in a solid material, larger refractive indices can be obtained and the resolution of the imaging system can be increased.

Abstract: Improvements in the fabrication of integrated circuits are driven by the decrease of the size of the features printed on the wafers. Current lithography techniques limits have been extended through the use of phase-shifting masks, off-axis illumination, and proximity effect correction. More recently, liquid immersion lithography has been proposed as a way to extend even further the limits of optical lithography. This invention described a methodology based on contact or proximity printing using a projection lens to define the image of the mask onto the wafer. As the imaging is performed in a solid material, larger refractive indices can be obtained and the resolution of the imaging system can be increased.

Abstract: Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the filled pattern to remove portions of the final material beyond dimensions of the layout elements.

Abstract: Systems and methods of semiconductor device optimization include a system and method to determine a dataset for a layer of the semiconductor device, where the operation includes receiving a dataset defining a plurality of original patterns of sacrificial material in a layer of a semiconductor device, wherein the original patterns of sacrificial material are used to define placement of spacer material to define patterning of circuit elements for the semiconductor device; determining densities of the plurality of original patterns of sacrificial material in areas across a portion of the layer of the semiconductor device; and augmenting the dataset to include an additional pattern of sacrificial material in an area of the layer having a density lower than a threshold density.

Abstract: Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.

Abstract: Various systems and methods related to semiconductor devices having a plurality of layers and having a first conductive trace on a first layer electrically connected to a second conductive trace on a second layer and electrically isolated from a third electrical trace on the second layer are provided. A semiconductor structure can include first, second and third layers. The first conducting layer may be etched to form a first trench for the first conductive trace. A layer of material on the second layer in the first trench can define a patch area, wherein the patch area is disposed in a location where the first trench crosses over the third electrical trace. A second trench may be etched in an area defined by the first trench and the patch area to remove material in the second layer exposed by the first trench, leaving material of the layer under the patch area.

Abstract: Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the filled pattern to remove portions of the final material beyond dimensions of the layout elements.

Abstract: Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the tilled pattern to remove portions of the final material beyond dimensions of the layout elements.

Abstract: Systems and methods of semiconductor device optimization include a system and method to determine a dataset for a layer of the semiconductor device, where the operation includes receiving a dataset defining a plurality of original patterns of sacrificial material in a layer of a semiconductor device, wherein the original patterns of sacrificial material are used to define placement of spacer material to define patterning of circuit elements for the semiconductor device; determining densities of the plurality of original patterns of sacrificial material in areas across a portion of the layer of the semiconductor device; and augmenting the dataset to include an additional pattern of sacrificial material in an area of the layer having a density lower than a threshold density.