Abstract: A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to generate a variable amplitude data output signal. Each stage is operable to increase or decrease a data signal, and each of the coefficient signals determines the magnitude of increase or decrease of the data input signal by a stage. A method for operating the mix mode driver includes generating the variable amplitude data output signal with one or more of the stages, and providing the variable amplitude data output signal to a trace.

Abstract: A method for a mix mode driver to accommodate traces of different lengths includes sequentially shifting values of a data signal to a number of stages and sequentially amplifying the values of the data signal at least one stage. Depending on the length of trace for the data signal, the method further includes providing at least one amplifying coefficient to at least one stage and coupling a subset of the stages to an adder. The method finally includes outputting the data signal from the adder to the trace.

Abstract: A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.

Abstract: A video processor for executing video processing operations. The video processor includes a host interface for implementing communication between the video processor and a host CPU. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A scalar execution unit is coupled to the host interface and the memory interface and is configured to execute scalar video processing operations. A vector execution unit is coupled to the host interface and the memory interface and is configured to execute vector video processing operations.

Abstract: A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.

Abstract: A new method to control differential signal trace impedance allows flexible use of different signal trace width and spacing while maintaining constant differential impedance in printed circuit boards. Differential impedance of a signal pair is determined by the geometry of individual traces and the spacing between traces. The value of the differential impedance is inversely proportional to signal trace width and directly proportional to signal trace spacing. By decreasing or increasing trace width and spacing simultaneously, a constant differential impedance can be achieved.

Abstract: A system and method of reducing wire-or glitch to improve bus speeds. In a system that supports wire-or functions, the rise time of the wave created by the off-going driver is controlled. The off-going wave is forced to climb gradually such that one propagation delay of the loaded bus later, it is only marginally above a high threshold voltage. The fall time of the wave created by an on-going driver is minimized such that a strong negative going voltage propagates down the bus. This strong negative going voltage drags a composite wave on the bus (i.e. the combination of the waves of the on-going driver and the off-going driver) back below a low threshold voltage approximately one propagation delay after the switching occurs.

Abstract: A method and apparatus for configuring the pinout of an integrated circuit. An integrated circuit includes an input/output structure including an input/output port. The input/output structure communicates a first signal in a first configuration and a second signal in a second configuration. The first and second signals are parallel signals of a bus.

Abstract: A component powered by a first power supply activates a driving signal. The driving signal indicates that both a second power supply voltage has a magnitude greater than a reference voltage and an enable signal is active. A driver transfers the output signal when the driving signal is active. In a multi-processor computer system implementation, each of two processor cores are independently supplied power by each of two core power supplies while a single I/O power supply supplies power to the I/O rings of both processors. Each processor includes a bus isolation circuit to prevent its respective processor from loading the system bus in the event that a core power supply fails.