Abstract: A single chip processor for use in a smart card has a plurality of instruction memory areas and a processor. Different instructions sets are selectively executable in response to a signal defining a memory area from which instructions are supplied. Preferably instruction and data memory areas are addressable as pages, wherein a page address cannot be directly accessed by a subset of instructions. The processor may include a central processing unit and a cryptographic logic unit which operate at different times and share common instruction memory and sequencing logic. Instructions are supplied to said cryptographic logic unit at an integer multiple of the rate at which they are supplied to said central processing unit.

Abstract: A liquid drop rate controller for controlling flow of fluid from an infusion fluid reservoir to an intravenous infusion site which includes a cam means in the form of a wheel mounted eccentrically on a shaft which varies the compression on a flexible tube carrying the liquid; the controller senses the actual drip rate optically and compares this to a preselected desired drip rate and varies the compression accordingly. The comparison is accomplished electronically by the generation of a time base whose frequency is controlled by the selected drip rate; this time base is compared to the actual drip rate observed by the optical sensing means, and the cam means is controlled in relation to an error signal obtained through the comparison. The controller includes a separate comparison circuit which comes into operation at low drip rates so as to increase accuracy of control.