Patents by Inventor Christopher J. Petti

Christopher J. Petti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150325310
    Abstract: A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.
    Type: Application
    Filed: July 20, 2015
    Publication date: November 12, 2015
    Applicant: SANDISK 3D LLC
    Inventors: Abhijit Bandyopadhyay, Tanmay Kumar, Scott Brad Herner, Christopher J. Petti, Roy E. Scheuerlein
  • Patent number: 9099385
    Abstract: Vertical 1T-1R memory cells, memory arrays of vertical 1T-1R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor and a resistivity-switching element coupled in series with and disposed above or below the vertical transistor. The vertical transistor includes a controlling electrode coupled to a word line that is above or below the vertical transistor. The controlling electrode is disposed on a sidewall of the vertical transistor. Each vertical transistor includes a first terminal coupled to a bit line, a second terminal comprising the controlling electrode coupled to a word line, and a third terminal coupled to the resistivity-switching element.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: August 4, 2015
    Assignee: SanDisk 3D LLC
    Inventor: Christopher J. Petti
  • Publication number: 20150131360
    Abstract: Vertical 1T-1R memory cells, memory arrays of vertical 1T-1R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor and a resistivity-switching element coupled in series with and disposed above or below the vertical transistor. The vertical transistor includes a controlling electrode coupled to a word line that is above or below the vertical transistor. The controlling electrode is disposed on a sidewall of the vertical transistor. Each vertical transistor includes a first terminal coupled to a bit line, a second terminal comprising the controlling electrode coupled to a word line, and a third terminal coupled to the resistivity-switching element.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: SanDisk 3D LLC
    Inventor: Christopher J. Petti
  • Patent number: 8969923
    Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: March 3, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Patent number: 8921686
    Abstract: A method to fabricate a photovoltaic device includes forming first and second contact regions at the first surface of a semiconductor donor body. A cleave plane may be formed by implanting ions into the donor body, and a lamina that includes the contact regions is cleaved from the donor body at the cleave plane. The first surface of the lamina may be contacted with a temporary support and fabricated into a photovoltaic device, wherein the lamina comprises the base of the photovoltaic device.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: December 30, 2014
    Assignee: GTAT Corporation
    Inventors: Steven M. Zuniga, Christopher J. Petti, Gopal Prabhu
  • Publication number: 20140328105
    Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.
    Type: Application
    Filed: July 17, 2014
    Publication date: November 6, 2014
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Patent number: 8871608
    Abstract: A method for fabricating a backside-illuminated sensor includes providing a thin film semiconductor lamina having a first conductivity, and forming a doped region having a second conductivity within the lamina and at a front surface of the lamina. The lamina may be provided as a free-standing lamina, or may be provided as a semiconductor donor body from which the lamina is cleaved. An electrical connection is formed to the doped region. A temporary carrier is contacted to the back surface of the semiconductor and later removed. A backside-illuminated sensor is fabricated from the semiconductor lamina, in which the thickness of the semiconductor lamina remains substantially unchanged during the fabrication process.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: October 28, 2014
    Assignee: GTAT Corporation
    Inventors: Venkatesan Murali, Arvind Chari, Gopal Prabhu, Christopher J. Petti
  • Patent number: 8822260
    Abstract: A novel surface texturing provides improved light-trapping characteristics for photovoltaic cells. The surface is asymmetric and includes shallow slopes at between about 5 and about 30 degrees from horizontal as well as steeper slopes at about 70 degrees or more from horizontal. It is advantageously used as either the front or back surface of a thin semiconductor lamina, for example between about 1 and about 20 microns thick, which comprises at least the base or emitter of a photovoltaic cell. In embodiments of the present invention, the shallow slopes are formed using imprint photolithography.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: September 2, 2014
    Assignee: GTAT Corporation
    Inventor: Christopher J. Petti
  • Publication number: 20140241031
    Abstract: In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: SanDisk 3D LLC
    Inventors: Abhijit Bandyopadhyay, Tanmay Kumar, Scott Brad Herner, Christopher J. Petti, Roy E. Scheuerlein
  • Patent number: 8809128
    Abstract: The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: August 19, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Patent number: 8785294
    Abstract: A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: July 22, 2014
    Assignee: GTAT Corporation
    Inventors: Venkatesan Murali, Steve Babayan, Christopher J. Petti
  • Publication number: 20140166968
    Abstract: A nonvolatile memory cell is provided that includes a diode and a reversible resistance-switching element that includes a resistance-switching metal oxide or nitride, the metal oxide or nitride including only one metal. Numerous other aspects are provided.
    Type: Application
    Filed: February 19, 2014
    Publication date: June 19, 2014
    Applicant: SANDISK 3D LLC
    Inventors: Scott Brad Herner, Christopher J. Petti, Tanmay Kumar
  • Patent number: 8748859
    Abstract: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: June 10, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Kang-Jay Hsia, Christopher J Petti, Calvin K Li
  • Patent number: 8741768
    Abstract: A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive features, etching a void in the second dielectric material, wherein the etch stops on the first dielectric material, and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: June 3, 2014
    Assignee: SanDisk 3D LLC
    Inventor: Christopher J. Petti
  • Patent number: 8741696
    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: June 3, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Publication number: 20140133074
    Abstract: An electronic device comprising a cover plate is disclosed. The cover plate comprises one or more sapphire layers having a thickness of less than 50 microns. Also disclosed are methods for preparing these ultrathin sapphire layers using an ion implantation/exfoliation method.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 15, 2014
    Applicant: GTAT CORPORATION
    Inventors: James M. Zahler, Christopher J. Petti
  • Patent number: 8687410
    Abstract: A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state, wherein the second programmed resistivity state stores a data state of the memory cell. Numerous other aspects are provided.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: April 1, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Scott Brad Herner, Christopher J. Petti, Tanmay Kumar
  • Publication number: 20140038329
    Abstract: Methods and apparatus are provided for forming an electronic device from a lamina and an epitaxially grown semiconductor material. The method includes providing a donor body comprising a top surface, epitaxially growing a semiconductor material on the top surface and implanting the top surface of the donor body with an ion dosage to form a cleave plane. After implantation, a lamina may be exfoliated from the donor body, wherein the top surface of the donor body becomes a first surface of the lamina. Exfoliating the lamina forms a second surface of the lamina, wherein the first surface is opposite the second surface. A metal support may be constructed on the lamina.
    Type: Application
    Filed: August 1, 2013
    Publication date: February 6, 2014
    Applicant: GTAT Corporation
    Inventor: Christopher J. Petti
  • Publication number: 20140030836
    Abstract: A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Applicant: Twin Creeks Technologies, Inc.
    Inventors: Venkatesan Murali, Steve Babayan, Christopher J. Petti
  • Patent number: 8633374
    Abstract: In aspects of the present invention, a lamina is formed having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: January 21, 2014
    Assignee: GTAT Corporation
    Inventors: Mohamed M. Hilali, Christopher J. Petti, S. Brad Herner