Patents by Inventor Christopher James Kapusta
Christopher James Kapusta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150099948Abstract: A flexible embedded sensor array includes a first substrate, an electrically conductive pad disposed on at least a portion of the first substrate, and a plurality of sensors disposed on at least a portion of electrically conductive pads. Further, the flexible embedded sensor array includes an electrically non-conductive adhesive material disposed in proximity to one or more of the plurality of sensors, a second substrate, and an electrical contact disposed between at least a portion of the sensor and at least a portion of the second substrate.Type: ApplicationFiled: October 4, 2013Publication date: April 9, 2015Applicant: General Electric CompanyInventors: Christopher James Kapusta, Eric Patrick Davis, Jason Harris Karp
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Patent number: 8940582Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.Type: GrantFiled: August 19, 2013Date of Patent: January 27, 2015Assignee: General Electric CompanyInventors: James Sabatini, Christopher James Kapusta, Glenn Forman
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Patent number: 8748754Abstract: A system and method of forming a patterned conformal structure for an electrical system is disclosed. The conformal structure includes a dielectric coating shaped to conform to a surface of an electrical system, with the dielectric coating having a plurality of openings therein positioned over contact pads on the surface of the electrical system. The conformal structure also includes a patterned conductive coating layered on the dielectric coating and on the contact pads such that an electrical connection is formed between the patterned conductive coating and the contact pads. The patterned conductive coating comprises at least one of an interconnect system, a shielding structure, and a thermal path.Type: GrantFiled: November 22, 2011Date of Patent: June 10, 2014Assignee: General Electric CompanyInventors: Christopher James Kapusta, Donald Paul Cunningham
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Patent number: 8742646Abstract: An ultrasound acoustic assembly includes a number of ultrasound acoustic arrays, each array comprising an acoustic stack comprising a piezoelectric layer assembled with at least one acoustic impedance dematching layer and with a support layer. The acoustic stack defines a number of dicing kerfs and a number of acoustic elements, such that the dicing kerfs are formed between neighboring ones of the acoustic elements. The dicing kerfs extend through the piezoelectric layer and through the acoustic impedance dematching layer(s) but extend only partially through the support layer. The ultrasound acoustic assembly further includes a number of application specific integrated circuit (ASIC) die. Each ultrasound acoustic array is coupled to a respective ASIC die to form a respective acoustic-electric transducer module. Methods of manufacture are also provided.Type: GrantFiled: March 29, 2012Date of Patent: June 3, 2014Assignee: General Electric CompanyInventors: Robert Gideon Wodnicki, Charles Edward Baumgartner, David Martin Mills, Kevin Matthew Durocher, William Hullinger Huber, George Charles Sogoian, Christopher James Kapusta
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Publication number: 20130344653Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.Type: ApplicationFiled: August 19, 2013Publication date: December 26, 2013Applicant: General Electric CompanyInventors: James Sabatini, Christopher James Kapusta, Glenn Forman
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Publication number: 20130257224Abstract: An ultrasound acoustic assembly includes a number of ultrasound acoustic arrays, each array comprising an acoustic stack comprising a piezoelectric layer assembled with at least one acoustic impedance dematching layer and with a support layer. The acoustic stack defines a number of dicing kerfs and a number of acoustic elements, such that the dicing kerfs are formed between neighboring ones of the acoustic elements. The dicing kerfs extend through the piezoelectric layer and through the acoustic impedance dematching layer(s) but extend only partially through the support layer. The ultrasound acoustic assembly further includes a number of application specific integrated circuit (ASIC) die. Each ultrasound acoustic array is coupled to a respective ASIC die to form a respective acoustic-electric transducer module. Methods of manufacture are also provided.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Applicant: GENERAL ELECTRIC COMPANYInventors: Robert Gideon Wodnicki, Charles Edward Baumgartner, David Martin Mills, Kevin Matthew Durocher, William Hullinger Huber, George Charles Sogoian, Christopher James Kapusta
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Patent number: 8536700Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.Type: GrantFiled: May 5, 2011Date of Patent: September 17, 2013Assignee: General Electric CompanyInventors: James Sabatini, Christopher James Kapusta, Glenn Forman
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Patent number: 8276268Abstract: A system and method of forming a patterned conformal structure for an electrical system is disclosed. The conformal structure includes a dielectric coating shaped to conform to a surface of an electrical system, with the dielectric coating having a plurality of openings therein positioned over contact pads on the surface of the electrical system. The conformal structure also includes a patterned conductive coating layered on the dielectric coating and on the contact pads such that an electrical connection is formed between the patterned conductive coating and the contact pads. The patterned conductive coating comprises at least one of an interconnect system, a shielding structure, and a thermal path.Type: GrantFiled: November 3, 2008Date of Patent: October 2, 2012Assignee: General Electric CompanyInventors: Christopher James Kapusta, Donald Paul Cunningham
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Publication number: 20120171816Abstract: An integrated circuit package includes a first dielectric layer comprising a dielectric film having a first side and a second side, the first side having a plurality of contact locations and a plurality of non-contact locations. The package includes a plurality of components, each component having a first surface and a second surface, wherein the first surface of each of the plurality of components is affixed to a corresponding one of the plurality of contact locations of the dielectric film absent a layer of adhesive therebetween that is distinct from a material of the dielectric film.Type: ApplicationFiled: December 15, 2011Publication date: July 5, 2012Inventors: Christopher James Kapusta, Glenn Forman, James Sabatini
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Publication number: 20120168941Abstract: An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip layer also comprises a first plurality of feed-thru pads coupled to the first side of the first flex layer and a first encapsulant encapsulating the first component, the first encapsulant having a portion thereof removed to form a first plurality of cavities in the first encapsulant and to expose the first plurality of feed-thru pads by way of the first plurality of cavities.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Inventors: Christopher James Kapusta, James Sabatini
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Patent number: 8163596Abstract: An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip layer also comprises a first plurality of feed-thru pads coupled to the first side of the first flex layer and a first encapsulant encapsulating the first component, the first encapsulant having a portion thereof removed to form a first plurality of cavities in the first encapsulant and to expose the first plurality of feed-thru pads by way of the first plurality of cavities.Type: GrantFiled: March 24, 2009Date of Patent: April 24, 2012Assignee: General Electric CompanyInventors: Christopher James Kapusta, James Sabatini
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Publication number: 20120080414Abstract: A method for laser patterning a sample is presented. The method includes coating at least one side of a substrate to form a sample, where coating the at least one side of the substrate forms an interface between the coating and the at least one side of the substrate. Further, the method includes configuring a scanning pattern for patterning the sample. In addition, the method includes determining settings for one or more laser beams of a laser based on the configured scanning pattern. Moreover, the method includes focusing the one or more laser beams of the laser at or near a surface of the substrate by selecting a focal point of the one or more laser beams near the surface of the substrate and setting a scribe depth near the surface of the substrate. The method also includes patterning the sample based on the configured scanning pattern using the one or more laser beams to generate one or more pixelated devices from the sample.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: GENERAL ELECTRIC COMPANYInventors: Wenwu Zhang, Christopher James Kapusta, Floribertus P. M. Heukensfeldt Jansen, Kristian William Andreini, Vladimir A. Lobastov, Kristen Ann Wangerin, Jun Cui
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Publication number: 20120069523Abstract: A system and method of forming a patterned conformal structure for an electrical system is disclosed. The conformal structure includes a dielectric coating shaped to conform to a surface of an electrical system, with the dielectric coating having a plurality of openings therein positioned over contact pads on the surface of the electrical system. The conformal structure also includes a patterned conductive coating layered on the dielectric coating and on the contact pads such that an electrical connection is formed between the patterned conductive coating and the contact pads. The patterned conductive coating comprises at least one of an interconnect system, a shielding structure, and a thermal path.Type: ApplicationFiled: November 22, 2011Publication date: March 22, 2012Inventors: Christopher James Kapusta, Donald Paul Cunningham
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Patent number: 8115117Abstract: A system and method of forming a patterned conformal structure for an electrical system is disclosed. The conformal structure includes a dielectric coating positioned on an electrical system having circuit components mounted thereon, the dielectric coating shaped to conform to a surface of the electrical system and having a plurality of openings therein positioned over contact pads on the surface of the electrical system. The conformal structure also includes a conductive coating layered on the dielectric coating and on the contact pads such that an electrical connection is formed between the conductive coating and the contact pads. The dielectric coating and the conductive coating have a plurality of overlapping pathway openings formed therethrough to isolate a respective shielding area of the conformal structure over desired circuit components or groups of circuit components.Type: GrantFiled: June 22, 2009Date of Patent: February 14, 2012Assignee: General Electric CompanyInventors: Christopher James Kapusta, Donald Paul Cunningham
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Patent number: 8026608Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.Type: GrantFiled: March 24, 2009Date of Patent: September 27, 2011Assignee: General Electric CompanyInventors: James Sabatini, Christopher James Kapusta, Glenn Forman
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Publication number: 20110210440Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.Type: ApplicationFiled: May 5, 2011Publication date: September 1, 2011Inventors: James Sabatini, Christopher James Kapusta, Glenn Forman
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Patent number: 7993064Abstract: A high temperature optoelectronic device package includes a substrate, an optoelectronic die situated on an upper surface of the substrate, a seal surrounding the optoelectronic die and situated on the upper surface of the substrate and a housing disposed on the seal having a ferrule-seating portion. The housing is disposed on the seal such that a fiber optic center of the ferrule-seating portion is aligned with an active portion of the optoelectronic die. The optoelectronic die is in operative communication with electronic traces of the substrate.Type: GrantFiled: April 1, 2008Date of Patent: August 9, 2011Assignee: General Electric CompanyInventors: David Mulford Shaddock, Christopher James Kapusta, Glen Peter Koste
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Publication number: 20110156261Abstract: An integrated circuit package includes a first dielectric layer comprising a dielectric film having a first side and a second side, the first side having a plurality of contact locations and a plurality of non-contact locations. The package includes a plurality of components, each component having a first surface and a second surface, wherein the first surface of each of the plurality of components is affixed to a corresponding one of the plurality of contact locations of the dielectric film absent a layer of adhesive therebetween that is distinct from a material of the dielectric film.Type: ApplicationFiled: March 24, 2009Publication date: June 30, 2011Inventors: Christopher James Kapusta, Glenn Forman, James Sabatini
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Patent number: 7952187Abstract: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.Type: GrantFiled: March 31, 2008Date of Patent: May 31, 2011Assignee: General Electric CompanyInventors: Christopher James Kapusta, Donald Cunningham, Richard Joseph Saia, Kevin Durocher, Joseph Iannotti, William Hawkins
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Patent number: 7952196Abstract: An interconnect assembly for use in high frequency applications includes an interconnect structure, a plurality of electronic die disposed on the interconnect structure, and an encapsulant at least partially surrounding the plurality of electronic die. The interconnect structure includes a plurality of layers. The interconnect assembly further includes a thermal management layer disposed within a portion of the encapsulant and proximate to the plurality of electronic die and a controlled impedance interconnect connected to the interconnect structure and extending to a peripheral surface of the interconnect assembly.Type: GrantFiled: April 21, 2008Date of Patent: May 31, 2011Assignee: Lockheed Martin CorporationInventors: Joseph Alfred Iannotti, Kevin Matthew Durocher, Christopher James Kapusta