Abstract: An A/D converter includes multiple bin comparators that compare an analog voltage to corresponding bin threshold voltages to provide output signals for providing corresponding comparison results. Some of the comparators includes enable inputs that selectively enable the output signal of the bin comparator to provide the corresponding comparison result based on a corresponding comparison result from at least one other bin comparator. The A/D convertor includes an encoder that utilizes the output signals to provide encoded bit values of the digital output. The A/D converter includes a bin selection circuit that utilizes the output signals to select a voltage level based on the output signals and provides the selected voltage level to a next stage of the A/D convertor. The next stage uses the selected voltage level and the analog voltage to provide at least one lessor bit of the digital output.

Abstract: An A/D converter includes multiple bin comparators that compare an analog voltage to corresponding bin threshold voltages to provide output signals for providing corresponding comparison results. Some of the comparators includes enable inputs that selectively enable the output signal of the bin comparator to provide the corresponding comparison result based on a corresponding comparison result from at least one other bin comparator. The A/D convertor includes an encoder that utilizes the output signals to provide encoded bit values of the digital output. The A/D converter includes a bin selection circuit that utilizes the output signals to select a voltage level based on the output signals and provides the selected voltage level to a next stage of the A/D convertor. The next stage uses the selected voltage level and the analog voltage to provide at least one lessor bit of the digital output.

Abstract: A circuit includes a first external terminal, a first lower resolution analog-to-digital converter (LRADC) coupled to the external terminal and configured to perform a first conversion of an analog signal received at the external terminal to a digital value, and a higher resolution analog-to-digital converter (HRADC). The HRADC is configured to selectively receive the analog signal from the first external terminal based on the digital value. When the digital value outputted by the first LRADC indicates a change in value of the received analog signal, the HRADC is provided with the analog signal and performs a second conversion of the analog signal to a second digital value. The first LRADC has a lower conversion resolution as compared to the HRADC.

Abstract: A comparator circuit includes a first transistor have a control electrode coupled to a first input voltage, a first current electrode coupled to a second input voltage, and a second current electrode coupled to a first circuit node. The circuit also includes a first inverter coupled to a first voltage supply terminal and having a first input coupled to the first circuit node and an output, a second transistor having a control electrode coupled to the output of the first inverter, and an active resistive element coupled in series between the first circuit node and a first current electrode of the second transistor.

Abstract: A comparator circuit includes a first transistor have a control electrode coupled to a first input voltage, a first current electrode coupled to a second input voltage, and a second current electrode coupled to a first circuit node. The circuit also includes a first inverter coupled to a first voltage supply terminal and having a first input coupled to the first circuit node and an output, a second transistor having a control electrode coupled to the output of the first inverter, and an active resistive element coupled in series between the first circuit node and a first current electrode of the second transistor.

Abstract: Input/output circuitry includes a first PMOS device and a first NMOS device having first current electrodes are connected to each other and a pad. First selection circuitry, when the I/O circuitry is disabled, provides a first supply voltage to a control electrode and an N-well of the first PMOS device when the pad voltage is between the first and second supply voltages and to directly provide the pad voltage to the control electrode and the N-well of the first PMOS device when the pad voltage is greater than the first supply voltage. Similarly, second selection circuitry, when the I/O circuitry is disabled, provides a second supply voltage or directly provides the pad voltage to a control electrode and a P-well of the first NMOS device depending on whether the pad voltage is between the first and second supply voltages or less than the second supply voltage, respectively.