Patents by Inventor Christopher Lawrence Rexer

Christopher Lawrence Rexer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140203355
    Abstract: In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.
    Type: Application
    Filed: March 24, 2014
    Publication date: July 24, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Christopher Boguslaw Kocon, Steven Sapp, Paul Thorup, Dean Probst, Robert Herrick, Becky Losee, Hamza Yilmaz, Christopher Lawrence Rexer, Daniel Calafut
  • Patent number: 8686493
    Abstract: A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: April 1, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Paul Thorup, Christopher Lawrence Rexer
  • Patent number: 8680611
    Abstract: In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 25, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Christopher Boguslaw Kocon, Steven Sapp, Paul Thorup, Dean Probst, Robert Herrick, Becky Losee, Hamza Yilmaz, Christopher Lawrence Rexer, Daniel Calafut
  • Patent number: 8669623
    Abstract: A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: March 11, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, Christopher Lawrence Rexer
  • Publication number: 20120319197
    Abstract: In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.
    Type: Application
    Filed: August 30, 2012
    Publication date: December 20, 2012
    Inventors: Christopher Boguslaw Kocon, Steven Sapp, Paul Thorup, Dean Probst, Robert Herrick, Becky Losee, Hamza Yilmaz, Christopher Lawrence Rexer, Daniel Calafut
  • Publication number: 20120156845
    Abstract: A method for forming a field effect transistor and Schottky diode includes forming a well region in a first portion of a silicon region where the field effect transistor is to be formed but not in a second portion of the silicon region where the Schottky diode is to be formed. Gate trenches are formed extending into the silicon region. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. Exposed surfaces of the well region are recessed to form a recess between every two adjacent trenches. Without masking any portion of the active area, a zero-degree blanket implant is performed to form a heavy body region of the second conductivity type in the well region between every two adjacent trenches.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 21, 2012
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Christopher Boguslaw Kocon, Steven Sapp, Paul Thorup, Dean Probst, Robert Herrick, Becky Losee, Hamza Yilmaz, Christopher Lawrence Rexer, Daniel Calafut
  • Publication number: 20110089432
    Abstract: An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer.
    Type: Application
    Filed: December 21, 2010
    Publication date: April 21, 2011
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Richard L. Woodin, Christopher Lawrence Rexer, Praveen Muraleedharan Shenoy, Kwanghoon Oh, Chongman Yun
  • Publication number: 20100320534
    Abstract: A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.
    Type: Application
    Filed: August 27, 2010
    Publication date: December 23, 2010
    Inventors: James Pan, Christopher Lawrence Rexer
  • Publication number: 20090315083
    Abstract: A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.
    Type: Application
    Filed: June 20, 2008
    Publication date: December 24, 2009
    Inventors: James Pan, Christopher Lawrence Rexer
  • Publication number: 20090315040
    Abstract: A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device.
    Type: Application
    Filed: August 6, 2009
    Publication date: December 24, 2009
    Inventors: Joseph A. Yedinak, Richard L. Woodin, Christopher Lawrence Rexer, Praveen Muraleedharan Shenoy, Kwanghoon Oh, Chongman Yun
  • Patent number: 7586156
    Abstract: A wide bandgap device in parallel with a device having a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: September 8, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Richard L. Woodin, Christopher Lawrence Rexer, Praveen Muraleedharan Shenoy, Kwanghoon Oh, Chongman Yun
  • Publication number: 20090111227
    Abstract: A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region.
    Type: Application
    Filed: December 30, 2008
    Publication date: April 30, 2009
    Inventors: Christopher Boguslaw Kocon, Steven Sapp, Paul Thorup, Dean Probst, Robert Herrick, Becky Losee, Hamza Yilmaz, Christopher Lawrence Rexer, Daniel Calafut
  • Publication number: 20090090966
    Abstract: A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 9, 2009
    Inventors: PAUL THORUP, Christopher Lawrence Rexer
  • Patent number: 7504306
    Abstract: A monolithically integrated field effect transistor and Schottky diode includes gate trenches extending into a semiconductor region. Source regions having a substantially triangular shape flank each side of the gate trenches. A contact opening extends into the semiconductor region between adjacent gate trenches. A conductor layer fills the contact opening to electrically contact: (a) the source regions along at least a portion of a slanted sidewall of each source region, and (b) the semiconductor region along a bottom portion of the contact opening, wherein the conductor layer forms a Schottky contact with the semiconductor region.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: March 17, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Steven Sapp, Hamza Yilmaz, Christopher Lawrence Rexer, Daniel Calafut
  • Patent number: 6080614
    Abstract: A method of fabricating a MOS-gated semiconductor device in which arsenic dopant is implanted through a mask to form a first layer, boron dopant is implanted through the mask to form a second layer deeper than the first layer, and in which a single diffusion step diffuses the implanted arsenic and the implanted boron at the same time to form a P+ body region with an N+ source region therein and a P type channel region.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: June 27, 2000
    Inventors: John Manning Sauidge Neilson, Linda Susan Brush, Frank Stensney, John Lawrence Benjamin, Anup Bhalla, Christopher Lawrence Rexer, Richard Douglas Stokes, Christopher Boguslow Kocon, Louise E. Skurkey, Christopher Michael Scarba
  • Patent number: 5877044
    Abstract: A gate electrode control structure of an MOS-gated semiconductor device includes four doped regions including a first (source) region forming a first P-N junction with an enclosing composite region comprising a second, lightly doped (channel) region wholly enclosing a third heavily doped (body) region partly enclosing the first region, and a fourth (drain) region forming a P-N junction with the third region. The gate electrode control structure is fabricated using known gate electrode self-alignment doping processes but wherein, in the process for forming the third heavily doped region, a spacer layer is provided on the gate electrode for defining a spacing between the third region and the channel region with an improved degree of precision.
    Type: Grant
    Filed: March 11, 1997
    Date of Patent: March 2, 1999
    Assignee: Harris Corporation
    Inventors: John Manning Savidge Neilson, Christopher Boguslaw Kocon, Richard Douglas Stokes, Linda Susan Brush, John Lawrence Benjamin, Louise Ellen Skurkey, Christopher Lawrence Rexer