Abstract: A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.

Abstract: The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.

Abstract: A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.

Abstract: A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type.

Abstract: A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.

Abstract: A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.

Abstract: A system and method for providing real-time, dynamic switching between first and second service providers each capable of providing a service for users over a communications network. The method includes steps of: establishing switching criterion for deciding when to switch service provision between the first service provider and second service provider; maintaining state information associated with a user's use of the service provided by a first service provider; switching between the first and second service provided over the communications network based on satisfaction of the switching criterion; and, migrating any state information maintained up to the time of switching to the second service. Preferably, the dynamic switching occurs in a manner substantially transparent to the user.

Abstract: A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type.

Abstract: A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.

Abstract: The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.

Abstract: A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.

Abstract: A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the packets to implement protocol conversion and generates converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the SoC macro core. The process of protocol conversion contained within the SoC macro core does not require the processing resources of a host system. The system-on chip macro core includes a bridge device for coupling a local bus in the protocol converting multiprocessor SoC macro core local bus to peripheral interfaces coupled to a system bus.

Abstract: A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.

Abstract: An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via high-speed interconnect, and each processor's memory is globally accessible by other processors. Each processor has multiple threads, each capable of fully executing programs. Each processors contains embedded dynamic random access memory (DRAM). Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify relates frames. Related frames are dispatch to the same thread so as to minimize the overhead associated with memory accesses and general protocol processing.

Abstract: A data communication controller processes incoming data frames. The controller includes a pre-processing block for receiving data frames and a frame processing unit coupled to the pre-processing block. The pre-processing block is configured to compare header fields of a current frame with header fields of a previous frame. The pre-processing block provides an output signal to the frame processing unit on the basis of the comparison of the header fields of the current and previous frames. The controller may operate in accordance with the Fiber Channel protocol, and the output signal may include bits to indicate that the current frame is of the same exchange, of the same sequence, and is next in sequence relative to the previous frame.

Abstract: A network handler uses a DMA device to assign packets to network processors in accordance with a mapping function which classifies packets based on its content, e.g., bits in one or more header fields. Preferably, the mapping function is implemented as a hash function, which uses a predetermined number of bits from packet as inputs. The result of this function specifies the processor to which the packet is assigned. To make implementation manageable in a high-traffic environment, each processor may be equipped with a queue, which holds pointer information. Such a pointer provides an indication of the area in memory where incoming packet resides. The network handler is particularly useful in a Fiber Channel environment, where the hash function may be implemented to assign all packets from the same sequence to the same processor, thereby resulting in improved processing efficiency.

Abstract: A data communication controller processes incoming data frames. The controller includes a pre-processing block for receiving data frames and a frame processing unit coupled to the pre-processing block. The pre-processing block is configured to compare header fields of a current frame with header fields of a previous frame. The pre-processing block provides an output signal to the frame processing unit on the basis of the comparison of the header fields of the current and previous frames. The controller may operate in accordance with the Fibre Channel protocol, and the output signal may include bits to indicate that the current frame is of the same exchange, of the same sequence, and is next in sequence relative to the previous frame.

Abstract: A network handler uses a DMA device to assign packets to network processors in accordance with a mapping function which classifies packets based on its content, e.g., bits in one or more header fields. Preferably, the mapping function is implemented as a hash function, which uses a predetermined number of bits from packet as inputs. The result of this function specifies the processor to which the packet is assigned. To make implementation manageable in a high-traffic environment, each processor may be equipped with a queue, which holds pointer information. Such a pointer provides an indication of the area in memory where incoming packet resides. The network handler is particularly useful in a Fibre Channel environment, where the hash function may be implemented to assign all packets from the same sequence to the same processor, thereby resulting in improved processing efficiency.

Abstract: An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via high-speed interconnect, and each processor's memory is globally accessible by other processors. Each processor has multiple threads, each capable of fully executing programs. Each processor contains embedded dynamic random access memory (DRAM). Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify related frames. Related frames are dispatched to the same thread so as to minimize the overhead associated with memory accesses and general protocol processing.

Abstract: A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.