Abstract: A silicide gate contact is formed which is relatively thicker than silicide contacts formed over source/drain regions and shallow junction extensions. A metal layer is first deposited to form silicide over the polysilicon gate and the source/drain extension regions. The silicide is removed from the extension regions, forming shallow junctions, and a layer of silicide remains on the polysilicon gate. A second metal deposition step and silicidation step forms silicide contacts over the source/drain regions and the polysilicon gate. The resulting silicide gate contact is thicker than the resulting silicide contacts over the source/drain regions.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have a hydrogen concentration below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device.

Abstract: A method is provided of forming a semiconductor seed layer starting with a non-electrochemical deposition of an initial deposition of the seed layer. This is followed by a very slow deposition rate electrochemical deposition with an organic additive at the beginning of the plating process to overcome the initial thin seed coverage at the bottom and bottom sidewall of a feature. The electrochemical deposition plates at a very low rate initially followed by a low rate deposition to build up a thicker and more uniform seed layer at the bottom and bottom sidewall. In the meantime, this slow plating rate step only adds a small thickness to the top portion of the feature where non-electrochemical deposition seed coverage was initially thicker.

Abstract: Nickel silicidation of a gate electrode is controlled using a tungsten silicide barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of tungsten silicide thereon and an upper polycrystalline silicon layer on the tungsten silicide layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and the tungsten silicide barrier layer prevents nickel from reacting with the lower polycrystalline silicon layer.

Abstract: Copper or a low resistivity copper alloy is initially deposited to fill relatively narrow openings leaving relatively wider openings unfilled. A copper alloy having improved electromigration resistance with respect to copper is then selectively deposited to fill the relatively wider openings, thereby improving electromigration resistance without increasing narrow line resistance. Embodiments include annealing after filling the relatively narrow openings and before filling the relatively wider openings, thereby reducing void formation in narrow lines.

Abstract: An electroplating system is provided for seed layer covered semiconductor wafers. A plating chamber is provided with an inert primary anode connectible to a positive voltage source and a semiconductor wafer connector connectible to a negative voltage source. The plating chamber further contains a consumable ring secondary anode connectible to the positive voltage source such that, when the plating chamber is filled with a plating solution and a semiconductor wafer is connected to the semiconductor wafer connector and the voltages are connected, the seed layer on the semiconductor wafer will be plated by consuming the consumable ring secondary anode.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.

Abstract: An electroplating system is provided for semiconductor wafers which include a plating chamber having a consumable shielded secondary anode shielded by an inert anode from a semiconductor wafer connector. For a copper plating system the plating chamber has a consumable copper shielded anode shielded by an inert platinum anode from a semiconductor wafer connector.

Abstract: A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.

Abstract: A semiconductor device and method for manufacturing the semiconductor device employing mixed metal silicide technology is disclosed. A semiconductor device is provided having a doped silicon region, such as a source/drain. A first metal layer comprising aluminum and a second metal layer comprising nickel are deposited over the semiconductor device. The device is subjected to rapid thermal annealing. The resulting device has a mixed metal silicide layer over the doped silicon region, the mixed metal silicide layer and the doped silicon region having smooth interface between them.

Abstract: Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a plasma containing ammonia and nitrogen to create a clean surface region having increased nitrogen. Embodiments include treating the silicon nitride sidewall spacers with an ammonia and nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

Abstract: Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.

Abstract: A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; forming nickel silicide layers disposed on the source/drain regions and the gate electrode, and two etching steps. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The first etch is performed with a sulfuric peroxide mix to remove unreacted nickel, and the second etch is performed with an ammonia peroxide mix to remove nickel silicide formed over the first and second sidewall spacers.

Abstract: A copper interconnect is formed by creating an opening in a dielectric layer. Copper is then deposited in a non-conformal electroplating process to fill a portion of the opening. A second electroplating process is then performed to conformally deposit copper in the remaining unfilled portion of the opening. The resulting deposition of the copper is more uniform and planar, thereby facilitating subsequent planarization of the semiconductor device.

Abstract: Copper metalization is planarized by CMP employing a slurry which avoids scratching the copper surface and is highly selective to the underlying barrier layer. Embodiments include CMP a copper filled damascene opening using a slurry comprising about 0.2 to about 0.7 wt. % Al2O3 and about 0.2 to about 2 wt. % oxalic acid to achieve a RMS no greater than about 10 Å.

Abstract: A small plating solution reservoir of about 250-cc or less volume is used to provide plating of one wafer at a time with a precisely controlled, repeatable, plating solution. The reservoir is connected to basic plating solution and additives which are provided in desired concentrations by a valving and control system for single wafers and drained after the single wafer is plated.

Abstract: Cu metalized wafers are stored at elevated temperatures to substantially complete recrystalization, thereby enabling subsequent CMP with a high degree of wafer to wafer uniformity. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill one or more damascene openings in a plurality of wafers, placing the wafers in one or more cassettes, and storage-annealing the cassettes on shelves of a cabinet maintained at about 50° C. to about 200° C. in nitrogen for about 2 minutes to about 3 days.

Abstract: A small plating solution reservoir is used to provide plating of one wafer at a time with a precisely controlled, repeatable, plating solution. The reservoir is connected to basic plating solution and additives which are provided in desired concentrations by a valving and control system for single wafers and the plating solution passes through a filtration unit and is returned to the reservoir during plating or to a plating container after plating. The filtration unit filters particulates and by-products, but also filters additives which a control system replenishes.

Abstract: A multiple-layer interconnect structure in an integrated circuit, is formed using damascene techniques. A first layer interconnect has a first dielectric layer through which at least one first layer conductor extends. A second layer interconnect is then formed on the first layer interconnect. The second layer interconnect also includes a second layer dielectric through which at least one second layer conductor extends. However, the second layer interconnect is created by first forming a thick second later dielectric layer and then reducing the thickness of the second layer dielectric prior to a patterning step. As a result topographical irregularities that may have carried over to the second layer interconnect from the first layer interconnect are removed by providing a substantially planar surface on the second layer dielectric.